公开(公告)号：US10528286B2

公开(公告)日：2020-01-07

申请号：US15671128

申请日：2017-08-07

Applicant: SanDisk Technologies LLC

Inventor： Ravindra Arjun Madpur ,  Amandeep Kaur

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/38 ,  G06F13/42 ,  G11C7/10

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. A set of ports includes a first port and a second port. A first port includes a first plurality of electrical contacts and a second port includes a second plurality of electrical contacts. An on-die controller communicates via a set of ports to receive command and address information and to transfer data for data operations on an array of non-volatile memory cells. An on-die controller uses a first port to receive command and address information and to transfer data. An on-die controller uses a second port to transfer data but not to receive command and address information.

公开(公告)号：US10367493B1

公开(公告)日：2019-07-30

申请号：US16008640

申请日：2018-06-14

Applicant: SanDisk Technologies LLC

Inventor： Sravanti Addepalli ,  Ravindra Arjun Madpur ,  Sridhar Yadala

IPC: G11C7/22 ,  H03K5/156 ,  H03L7/089 ,  H03K5/133 ,  G06F1/08 ,  G06F1/10 ,  H03K5/00

Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

公开(公告)号：US10528255B2

公开(公告)日：2020-01-07

申请号：US15365944

申请日：2016-11-30

Applicant: SanDisk Technologies LLC

Inventor： Jiwang Lee ,  Anil Pai ,  Tianyu Tang ,  Ravindra Arjun Madpur ,  Amandeep Kaur ,  Ragul Kumar Krishnan ,  Venkata Kolagatla

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.

公开(公告)号：US20190195948A1

公开(公告)日：2019-06-27

申请号：US15852407

申请日：2017-12-22

Applicant: SanDisk Technologies LLC

Inventor： Amandeep Kaur ,  Sridhar Yadala ,  Jayanth Mysore Thimmaiah ,  Ravindra Arjun Madpur

IPC: G01R31/319 ,  G05B17/02 ,  G06F17/50 ,  G05B23/02 ,  G11C11/4072 ,  G11C29/02 ,  G11C29/50 ,  G11C7/20

Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.

公开(公告)号：US10361690B1

公开(公告)日：2019-07-23

申请号：US16008678

申请日：2018-06-14

Applicant: SanDisk Technologies LLC

Inventor： Sravanti Addepalli ,  Ravindra Arjun Madpur ,  Sridhar Yadala

IPC: H03K5/15 ,  H03K5/156 ,  G11C7/22 ,  H03L7/089 ,  G06F1/10 ,  G06F1/06 ,  H03K5/133 ,  H03K5/00

Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

公开(公告)号：US20180136878A1

公开(公告)日：2018-05-17

申请号：US15671128

申请日：2017-08-07

Applicant: SanDisk Technologies LLC

Inventor： Ravindra Arjun Madpur ,  Amandeep Kaur

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/38 ,  G06F13/42 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0625 ,  G06F3/0688 ,  G06F9/3871 ,  G06F13/1615 ,  G06F13/4239 ,  G11C7/10 ,  G11C7/1039 ,  G11C7/1072

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. A set of ports includes a first port and a second port. A first port includes a first plurality of electrical contacts and a second port includes a second plurality of electrical contacts. An on-die controller communicates via a set of ports to receive command and address information and to transfer data for data operations on an array of non-volatile memory cells. An on-die controller uses a first port to receive command and address information and to transfer data. An on-die controller uses a second port to transfer data but not to receive command and address information.

公开(公告)号：US10725104B2

公开(公告)日：2020-07-28

申请号：US15852407

申请日：2017-12-22

Applicant: SanDisk Technologies LLC

Inventor： Amandeep Kaur ,  Sridhar Yadala ,  Jayanth Mysore Thimmaiah ,  Ravindra Arjun Madpur

IPC: G01R31/28 ,  G01R31/319 ,  G05B17/02 ,  G05B23/02 ,  G11C29/02 ,  G11C11/4072 ,  G01R31/30 ,  G06F30/327 ,  G11C29/50 ,  G11C7/20 ,  G11C5/14

Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.

公开(公告)号：US10552169B2

公开(公告)日：2020-02-04

申请号：US15708121

申请日：2017-09-18

Applicant: SanDisk Technologies LLC

Inventor： Ravindra Arjun Madpur ,  Amandeep Kaur

IPC: G06F9/4401

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die signal calibration. A calibration circuit on an integrated circuit device receives data from an active data path of the integrated circuit device and detects a variation in the received data from a calibration data pattern. An adjustment circuit on an integrated circuit device reduces a delay of an active data path of the integrated circuit device in response to detecting a first variation in received data. An adjustment circuit on an integrated circuit device increases a delay of an active data path of the integrated circuit device in response to detecting a second variation in received data.

公开(公告)号：US10528267B2

公开(公告)日：2020-01-07

申请号：US15637298

申请日：2017-06-29

Applicant: SanDisk Technologies LLC

Inventor： Nidhi Batra ,  Ravindra Arjun Madpur ,  Amandeep Kaur

IPC: G06F3/06

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queueing commands for storage operations. An apparatus includes a command queue configured to queue storage commands received at a storage device and a controller for the storage device. A controller is configured to receive a storage command on a first port of a storage device. A controller is configured to queue a received storage command as an entry in a command queue. An entry in a command queue indicates a type of a received storage command. A controller is configured to service a received storage command from a command queue on a second port of a storage device based on a type of the received storage command indicated by an entry in the command queue associated with the received storage command.

公开(公告)号：US10204668B1

公开(公告)日：2019-02-12

申请号：US15727987

申请日：2017-10-09

Applicant: SanDisk Technologies LLC

Inventor： Sneha Bhatia ,  Amandeep Kaur ,  Ravindra Arjun Madpur

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/08

Abstract: Disclosed is a system including a memory timing calibration circuit to calibrate a strobe signal of a memory device and a method of calibrating the strobe signal. The memory timing calibration circuit includes a difference signal generator coupled to a strobe signal generator and an external control circuit. The difference signal generator is configured to generate a difference signal indicating a time difference between the strobe signal from the strobe signal generator and an external clock signal from the external control circuit. The memory timing calibration circuit further includes a delay circuit coupled to the difference signal generator and the external control circuit. The delay circuit is configured to generate a modified external clock signal by delaying the external clock signal by a delay determined based at least in part on the difference signal.