公开(公告)号：US5708607A

公开(公告)日：1998-01-13

申请号：US724886

申请日：1996-10-03

申请人： Sang Hyun Lee ,  Ha Min Sung

发明人： Sang Hyun Lee ,  Ha Min Sung

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  H03F3/45 ,  G11C7/00

CPC分类号： G11C7/1051

摘要： A data read circuit of a memory includes an inverting unit, a precharging unit, a first amplifying unit, a second amplifying unit, and an output buffer unit. The inverting unit inverts data from a sense amplifier, and the precharging unit precharges a data bus line to Vcc/2. The first amplifying unit receives and amplifies the inverted data, and the second amplifying unit is commonly connected to an input terminal of the first amplifying unit to receive and amplify the signal output from the inverting unit. The output buffer unit receives, inverts and outputs the signal amplified by the first and second amplifying units.

摘要翻译： 存储器的数据读取电路包括反相单元，预充电单元，第一放大单元，第二放大单元和输出缓冲单元。 反相单元从读出放大器反转数据，预充电单元将数据总线预充电到Vcc / 2。 第一放大单元接收并放大反相数据，第二放大单元共同连接到第一放大单元的输入端，以接收和放大从反相单元输出的信号。 输出缓冲器单元接收，反相和输出由第一和第二放大单元放大的信号。

公开(公告)号：US06570796B2

公开(公告)日：2003-05-27

申请号：US10032016

申请日：2001-12-31

申请人： Ha Min Sung

发明人： Ha Min Sung

IPC分类号： G11C700

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/5004

摘要： A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

摘要翻译： 晶片老化测试和用于半导体存储器件的晶片测试电路，其可以通过在晶片状态的探针测试中使用焊盘进行晶片老化测试，从而降低封装费用并提高F / T产量 。

公开(公告)号：US06657903B2

公开(公告)日：2003-12-02

申请号：US10028323

申请日：2001-12-28

申请人： Ha Min Sung

发明人： Ha Min Sung

IPC分类号： G11C700

CPC分类号： G11C5/143 ,  G11C5/146

摘要： A circuit for generating a power-up signal in a semiconductor memory device which can remove instability due to non-generation of a back bias voltage by detecting the back bias voltage of a memory cell internally generated when an external power voltage is applied, and detecting the external power voltage when the back bias voltage reaches a predetermined level, and which can improve the stability of the power-up signal by initializing an external power voltage detecting unit by using an initial start-up circuit.

摘要翻译： 一种用于在半导体存储器件中产生上电信号的电路，其可以通过检测当施加外部电源电压时内部产生的存储单元的反向偏压而消除由于不产生背偏压而产生的不稳定性，并且检测 当背偏压达到预定电平时的外部电源电压，并且可以通过使用初始启动电路来初始化外部电源电压检测单元来提高上电信号的稳定性。

公开(公告)号：US06281742B1

公开(公告)日：2001-08-28

申请号：US09247530

申请日：1999-02-10

申请人： Ha Min Sung

发明人： Ha Min Sung

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  H02M2001/0032 ,  H02M2003/078 ,  Y02B70/16

摘要： A substrate voltage detection control circuit is disclosed. The circuit includes a substrate voltage detector detecting a substrate voltage from a charge pump, and a control circuit separately operating the substrate voltage detector in accordance with an operation mode of a chip, for thereby sensitively reacting to the variation of the substrate voltage by turning on a substrate voltage detector in the active mode.

摘要翻译： 公开了一种基板电压检测控制电路。 该电路包括检测来自电荷泵的衬底电压的衬底电压检测器，以及根据芯片的操作模式分别操作衬底电压检测器的控制电路，从而通过开启来敏感地反应衬底电压的变化 处于活动模式的基板电压检测器。

公开(公告)号：US06711077B2

公开(公告)日：2004-03-23

申请号：US10412268

申请日：2003-04-14

申请人： Ha Min Sung

发明人： Ha Min Sung

IPC分类号： G11C700

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/5004

摘要： A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

摘要翻译： 晶片老化测试和用于半导体存储器件的晶片测试电路，其可以通过在晶片状态的探针测试中使用焊盘进行晶片老化测试，从而降低封装费用并提高F / T产量 。

公开(公告)号：US6147512A

公开(公告)日：2000-11-14

申请号：US300918

申请日：1999-04-28

申请人： Ha Min Sung ,  Jong Hoon Park

发明人： Ha Min Sung ,  Jong Hoon Park

IPC分类号： G11C11/417 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407 ,  G11C16/02 ,  G11C16/06 ,  H03K19/0175

CPC分类号： G11C7/1084 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096

摘要： An input buffer circuit includes a transition detecting unit for receiving an input signal, detecting a transition of the input signal, and outputting a detecting signal and a delayed input signal; a detecting signal summing unit for summing up the detecting signal and other detecting signals outputted from other transition detecting units, and outputting a plurality of summed signals; a buffer unit for transmitting the delayed input signal in accordance with the plurality of summed signals; a control signal generator for receiving one of the plurality of summed signals and a first control signal, and outputting a second control signal and a third control signal; and a write driver 204 for receiving the second and third control signals, and transmitting an output signal of the buffer unit to a cell by a trigger of the plurality of summed signals.

摘要翻译： 输入缓冲电路包括转换检测单元，用于接收输入信号，检测输入信号的转变，并输出检测信号和延迟的输入信号; 检测信号求和单元，用于对检测信号和从其他转变检测单元输出的其他检测信号相加，并输出多个相加信号; 缓冲单元，用于根据所述多个相加信号发送所述延迟的输入信号; 控制信号发生器，用于接收多个求和信号中的一个和第一控制信号，并输出第二控制信号和第三控制信号; 以及用于接收第二和第三控制信号的写驱动器204，并且通过多个相加信号的触发将缓冲器单元的输出信号发送到单元。