公开(公告)号：US08045448B2

公开(公告)日：2011-10-25

申请号：US12189931

申请日：2008-08-12

申请人： Kyu-Min Kang ,  Sang-In Cho ,  Sangsung Choi

发明人： Kyu-Min Kang ,  Sang-In Cho ,  Sangsung Choi

IPC分类号： H04J11/00

CPC分类号： H04L27/2647

摘要： Provided is an apparatus and method for detecting a packet of a zero-padded OFDM signal, which are capable of determining if a packet exists in a reception (RX) signal by comparing a cross-correlation value of an OFDM signal delayed by a predetermined sample time, e.g., a zero-padded sample time, with a power value of the RX signal, thereby increasing a packet detection probability and preventing a false alarm. The packet detecting apparatus includes: a cross-correlation calculator for calculating a cross-correlation value of a reception signal received from the outside and delaying the calculated cross-correlation value by a predetermined sample time; a power calculator for calculating a power value of the reception signal; and a packet detector for determining if a packet exists in the reception signal by comparing the delayed cross-correlation value with the calculated power value, and detecting the corresponding packet.

摘要翻译： 提供了一种检测零填充OFDM信号的分组的装置和方法，其能够通过比较延迟了预定样本的OFDM信号的互相关值来确定在接收（RX）信号中是否存在分组 时间，例如零填充采样时间，具有RX信号的功率值，从而增加分组检测概率并防止误报。 分组检测装置包括：互相关计算器，用于计算从外部接收的接收信号的互相关值，并将所计算的互相关值延迟预定采样时间; 功率计算器，用于计算接收信号的功率值; 以及分组检测器，用于通过将延迟的互相关值与所计算的功率值进行比较来确定接收信号中是否存在分组，并检测相应的分组。

公开(公告)号：US20100094920A1

公开(公告)日：2010-04-15

申请号：US12536240

申请日：2009-08-05

申请人： Sang In Cho ,  Kyu-Min Kang ,  Sangsung Choi

发明人： Sang In Cho ,  Kyu-Min Kang ,  Sangsung Choi

IPC分类号： G06F17/14

CPC分类号： G06F17/142

摘要： A Fourier transform device generates a first sequence according to an input sequence based on a stored lookup table, and generates an output sequence by performing a butterfly operation on the first sequence a plurality of times. Therefore, hardware capacity and power consumption of the Fourier transform device can be reduced

摘要翻译： 傅里叶变换装置根据存储的查找表根据输入序列生成第一序列，并且通过多次对第一序列执行蝶形运算来生成输出序列。 因此，可以降低傅里叶变换装置的硬件容量和功耗

公开(公告)号：US20090147667A1

公开(公告)日：2009-06-11

申请号：US12189931

申请日：2008-08-12

申请人： Kyu-Min KANG ,  Sang-In Cho ,  Sangsung Choi

发明人： Kyu-Min KANG ,  Sang-In Cho ,  Sangsung Choi

IPC分类号： H04J11/00

CPC分类号： H04L27/2647

摘要： Provided is an apparatus and method for detecting a packet of a zero-padded OFDM signal, which are capable of determining if a packet exists in a reception (RX) signal by comparing a cross-correlation value of an OFDM signal delayed by a predetermined sample time, e.g., a zero-padded sample time, with a power value of the RX signal, thereby increasing a packet detection probability and preventing a false alarm. The packet detecting apparatus includes: a cross-correlation calculator for calculating a cross-correlation value of a reception signal received from the outside and delaying the calculated cross-correlation value by a predetermined sample time; a power calculator for calculating a power value of the reception signal; and a packet detector for determining if a packet exists in the reception signal by comparing the delayed cross-correlation value with the calculated power value, and detecting the corresponding packet.

摘要翻译： 提供了一种检测零填充OFDM信号的分组的装置和方法，其能够通过比较延迟了预定样本的OFDM信号的互相关值来确定在接收（RX）信号中是否存在分组 时间，例如零填充采样时间，具有RX信号的功率值，从而增加分组检测概率并防止误报。 分组检测装置包括：互相关计算器，用于计算从外部接收的接收信号的互相关值，并将所计算的互相关值延迟预定采样时间; 功率计算器，用于计算接收信号的功率值; 以及分组检测器，用于通过将延迟的互相关值与所计算的功率值进行比较来确定接收信号中是否存在分组，并检测相应的分组。

公开(公告)号：US07953199B2

公开(公告)日：2011-05-31

申请号：US12610604

申请日：2009-11-02

申请人： Kyu-Min Kang ,  Sang In Cho ,  Sung Woo Choi ,  Sangsung Choi

发明人： Kyu-Min Kang ,  Sang In Cho ,  Sung Woo Choi ,  Sangsung Choi

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04B1/7183 ,  H04B1/7075

摘要： Provided is a synchronization error tracking device and method. The method and system estimates and corrects the synchronization error generated by time and frequency offsets during the data transmission interval and uses a module designed for initial synchronization or channel estimation without adding a new correlation operator. Further, a combining mark value and a synchronization position value acquired during the synchronization process are used.

摘要翻译： 提供了一种同步误差跟踪装置和方法。 该方法和系统估计并校正数据传输间隔期间由时间和频率偏移产生的同步误差，并使用设计用于初始同步或信道估计的模块，而不添加新的相关运算符。 此外，使用在同步处理期间获取的组合标记值和同步位置值。

公开(公告)号：USRE44413E1

公开(公告)日：2013-08-06

申请号：US12904718

申请日：2010-10-14

申请人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park

发明人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： H04B1/10

CPC分类号： H04B1/7176 ,  H04B1/7174 ,  H04B2201/70707

摘要： An FIR filter of a DS-CDMA UWB modem transmitter and a control method thereof are disclosed. The FIR filter includes an LUT control device for outputting a resultant value of “0” to all adders if data values corresponding to upper three chips H2, M2 and L2 and lower three chips H, M and L are “000000”, and discriminating which group between a first group and a second group the upper/lower data values belong to if the upper/lower data values are not“000000”. The LUT control device provides upper or lower LUT values to the adders using the upper or lower LUT values as they are, or converts the upper or lower LUT values into 2's complements and provides the converted values to the adders according to the discriminated first or second group.

摘要翻译： 公开了DS-CDMA UWB调制解调发射机的FIR滤波器及其控制方法。 FIR滤波器包括LUT控制装置，用于如果对应于上三个码片H2，M2和L2以及较低三个码片H，M和L的数据值为“000000”，则将所得到的值“0”输出到所有加法器，并且鉴别哪个 如果上/下数据值不是“000000”，则在第一组和第二组之间组合上/下数据值。 LUT控制装置使用上下LUT值向加法器提供上或下LUT值，或者将上或下LUT值转换为2的补码，并根据所识别的第一或第二值向加法器提供转换的值 组。

公开(公告)号：US07623562B2

公开(公告)日：2009-11-24

申请号：US11065570

申请日：2005-02-25

申请人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park ,  Chae Kyu Kim ,  Jeong Goo Lee

发明人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park ,  Chae Kyu Kim ,  Jeong Goo Lee

IPC分类号： H04B1/69

CPC分类号： H04B1/71637 ,  H04B1/7075 ,  H04B1/7183

摘要： Provided are an initial synchronization acquiring device and method in a parallel processed DS-CDMA UWB system and a DS-CDMA UWB system's receiver using the same. The initial synchronization acquiring device is constructed to include a correlator for correlating input signals and outputting correlation result values and an initial synchronizer for tuning initial symbol synchronization and frame synchronization by using the correlation result values received from the correlator and then storing combining mark values and a synchronization position value in a register, thereby making it possible to greatly decrease a system's complexity, compared to the existing method of separately designing respective modules for acquiring packet synchronization and symbol synchronization in the existing CDMA system. Also, the initial synchronization acquiring device and method additionally compensates a synchronization error caused by a frequency offset generated between clocks used by a transmitter and a receiver and thereby can be efficiently used in the high-speed and parallel-processed DS-CDMA UWB system.

摘要翻译： 提供了一种并行处理的DS-CDMA UWB系统中的初始同步获取装置和方法，以及使用其的DS-CDMA UWB系统的接收机。 初始同步获取装置被构造为包括用于使输入信号相关并输出相关结果值的相关器和用于通过使用从相关器接收的相关结果值来调整初始符号同步和帧同步的初始同步器，然后存储组合标记值和 与现有CDMA系统中分别设计用于获取分组同步和符号同步的各个模块的现有方法相比，寄存器中的同步位置值可以大大降低系统的复杂度。 此外，初始同步获取装置和方法还补偿由发射机和接收机使用的时钟之间产生的频率偏移引起的同步误差，从而可以在高速和并行处理的DS-CDMA UWB系统中有效地使用。

公开(公告)号：US07382822B2

公开(公告)日：2008-06-03

申请号：US11063583

申请日：2005-02-24

申请人： Bub Joo Kang ,  Kyu Min Kang ,  Sangsung Choi ,  Kwang Roh Park

发明人： Bub Joo Kang ,  Kyu Min Kang ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： H04B1/00

CPC分类号： H04B1/70735 ,  H04B1/7077 ,  H04B1/7183

摘要： There is provided a code acquisition device and method using a two-step search process in a DS-CDMA UWB modem. The device includes: an I/Q channel symbol generating unit for, generating a plurality (i) of nth I/Q channel symbols in a first search process and generating a plurality of nth I/Q channel symbols in a second search process; a spread code selecting unit for receiving the plurality of nth I/Q channel symbols in the first search process; an NNC2NS tap I/Q channel symbol matched filter unit for, in the second search process, receiving the plurality (i) of nth I/Q channel symbols; a switching unit for changing to a closed state of the second search process; and a super frame and symbol boundary time deciding unit for deciding a super frame time and a symbol boundary time.

摘要翻译： 提供了在DS-CDMA UWB调制解调器中使用两步搜索处理的代码获取装置和方法。 该装置包括：I / Q信道符号生成单元，用于在第一搜索处理中生成第n个第I / Q个信道符号的多个（i），并产生多个第n个 在第二搜索过程中的I / Q通道符号; 扩展码选择单元，用于在第一搜索处理中接收多个第n个I / Q信道符号; 用于在第二搜索过程中，接收多个（i）个第n个/第N个N / N个抽头I / Q通道符号匹配滤波器单元， SUB> I / Q通道符号; 用于切换到第二搜索处理的关闭状态的切换单元; 以及用于决定超帧时间和符号边界时间的超帧和符号边界时间决定单元。

公开(公告)号：US07693924B2

公开(公告)日：2010-04-06

申请号：US11264886

申请日：2005-11-02

申请人： Sang In Cho ,  Sangsung Choi ,  Kwang Roh Park

发明人： Sang In Cho ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： G06F17/14

CPC分类号： H04L27/265 ,  H04L27/263

摘要： A 2N-point and N-point FFT/IFFT dual mode processor is provided. The processor includes a butterfly operator, the first and second MUXs, and the first and second N-point FFT processors. The butterfly operator receives 2N data and butterfly-operates on the received 2N data when receiving a control signal ‘0’ from the controller. The first and second MUXs respectively receive results from the butterfly operator to output the results in an increment of N when receiving a control signal ‘0’ from the controller, and respectively outputs different N data when receiving a control signal ‘1’ from the controller. The first and second N-point FFT processors N-point FFT operate on the results from the first and second MUXs and respectively output the same under control of the controller. Since the N-point FFT operation can be simultaneously performed two times at a receiver, the performance of the receiver can be enhanced.

摘要翻译： 提供2N点和N点FFT / IFFT双模式处理器。 处理器包括蝶形运算符，第一和第二MUX以及第一和第二N点FFT处理器。 当从控制器接收到控制信号“0”时，蝶形运算符接收2N个数据并对接收的2N数据进行蝶形运算。 当从控制器接收到控制信号“0”时，第一和第二MUX分别接收蝶形运算器的结果以输出N的增量，并且当从控制器接收到控制信号“1”时分别输出不同的N数据 。 第一和第二N点FFT处理器N点FFT对来自第一和第二MUX的结果进行操作，并在控制器的控制下分别输出。 由于在接收机可以同时进行N点FFT运算两次，所以可以提高接收机的性能。

公开(公告)号：US07436915B2

公开(公告)日：2008-10-14

申请号：US11137468

申请日：2005-05-26

申请人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park

发明人： Kyu Min Kang ,  Bub Joo Kang ,  Sangsung Choi ,  Kwang Roh Park

IPC分类号： H04B1/10

CPC分类号： H04B1/7176 ,  H04B1/7174 ,  H04B2201/70707

摘要： An FIR filter of a DS-CDMA UWB modem transmitter and a control method thereof are disclosed. The FIR filter includes an LUT control device for outputting a resultant value of “0” to all adders if data values corresponding to upper three chips H2, M2 and L2 and lower three chips H, M and L are “000000”, and discriminating which group between a first group and a second group the upper/lower data values belong to if the upper/lower data values are not“000000”. The LUT control device provides upper or lower LUT values to the adders using the upper or lower LUT values as they are, or converts the upper or lower LUT values into 2's complements and provides the converted values to the adders according to the discriminated first or second group.

摘要翻译： 公开了DS-CDMA UWB调制解调发射机的FIR滤波器及其控制方法。 如果对应于上三个码片H 2，M 2和L 2以及较低的三个码片H，M和L的数据值为“000000”，则FIR滤波器包括LUT控制装置，用于向所有加法器输出结果值“0” 并且如果所述上/下数据值不是“000000”，则鉴别所述上/下数据值属于第一组和第二组之间的组。 LUT控制装置使用上下LUT值向加法器提供上或下LUT值，或者将上或下LUT值转换为2的补码，并根据所识别的第一或第二值向加法器提供转换的值 组。

公开(公告)号：US08774306B2

公开(公告)日：2014-07-08

申请号：US13217435

申请日：2011-08-25

申请人： Mi Kyung Oh ,  Cheol-ho Shin ,  Byoung Hak Kim ,  Seung Sik Lee ,  Sangsung Choi

发明人： Mi Kyung Oh ,  Cheol-ho Shin ,  Byoung Hak Kim ,  Seung Sik Lee ,  Sangsung Choi

IPC分类号： H04L27/10

CPC分类号： H04L27/12 ,  H04L25/4902

摘要： A transmitting apparatus groups a data bit sequence to groups each formed of a predetermined number of bits, modulates predetermined bits of one of groups through a frequency shift keying (FSK) modulation method, non-continuously aligns the FSK modulation signals, and transmits the non-continuous FSK modulation signals.

摘要翻译： 发送装置将数据比特序列分组成各自由预定比特数组成的组，通过频移键控（FSK）调制方式调制组中的一组的预定比特，不连续对准FSK调制信号， - 连续的FSK调制信号。