公开(公告)号：US20110291229A1

公开(公告)日：2011-12-01

申请号：US12831341

申请日：2010-07-07

Applicant: Sang-Jin BYEON ,  Jun-Gi Choi

Inventor： Sang-Jin BYEON ,  Jun-Gi Choi

IPC: H01L23/538 ,  H01L23/525 ,  H01L21/66

CPC classification number: H01L21/76879 ,  H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract translation: 半导体集成电路包括：半导体芯片; 通过芯片穿过设置在半导体芯片中的导电图案并切割导电图案; 以及设置在贯通芯片通孔的外周面上的绝缘图案，以使导电图案与贯通芯片通孔绝缘。

公开(公告)号：US20130043933A1

公开(公告)日：2013-02-21

申请号：US13592902

申请日：2012-08-23

Applicant: Sang-Jin BYEON

Inventor： Sang-Jin BYEON

IPC: G05F1/10

CPC classification number: G11C5/147

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

公开(公告)号：US20100141332A1

公开(公告)日：2010-06-10

申请号：US12429782

申请日：2009-04-24

Applicant: Sang-Jin BYEON

Inventor： Sang-Jin BYEON

IPC: G05F1/10

CPC classification number: G11C5/145

Abstract: An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.

Abstract translation: 半导体器件的内部电压发生器包括电荷泵送单元，用于基于参考电压的电压电平执行电荷泵浦操作，以产生具有高于外部电源电压的电压电平的电荷泵浦电压; 以及内部电压产生单元，用于基于相对于第一温度范围内的温度变化线性的内部电压电平进行电荷泵送操作以产生内部电压，并且基于该电压产生单元执行充电泵送操作 内部电压钳位电平，其在第二温度范围内与温度变化无关，以产生内部电压。

公开(公告)号：US20090257289A1

公开(公告)日：2009-10-15

申请号：US12165057

申请日：2008-06-30

Applicant: Sang-Jin BYEON

Inventor： Sang-Jin BYEON

IPC: G11C7/00 ,  G05F1/10

CPC classification number: G11C5/147

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

Abstract translation: 提供一种半导体器件，其包括内部电压发生器电路，其根据操作速度提供具有不同电平的内部电压。 半导体器件包括内部电压发生器电路，其被配置为接收操作速度信息以根据操作速度产生具有不同电平的内部电压; 以及使用内部电压工作的内部电路。

公开(公告)号：US20130162343A1

公开(公告)日：2013-06-27

申请号：US13620444

申请日：2012-09-14

Applicant: Sang-Jin BYEON

Inventor： Sang-Jin BYEON

IPC: H01L25/00

CPC classification number: H01L25/00 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system includes a first chip including a first node and configured to generate first identification information indicating the first chip in response to a voltage of the first node, a second chip including a second node and configured to generate second identification information indicating the second chip in response to a voltage of the second node, and a channel connected to the first node and the second node and generate a voltage difference between the first node and the second node.

Abstract translation: 集成电路系统包括：第一芯片，包括第一节点，并且被配置为响应于第一节点的电压产生指示第一芯片的第一识别信息;第二芯片，包括第二节点，并且被配置为产生指示第二节点的第二标识信息 响应于第二节点的电压的芯片，以及连接到第一节点和第二节点的信道，并且在第一节点和第二节点之间产生电压差。

公开(公告)号：US20100091583A1

公开(公告)日：2010-04-15

申请号：US12640883

申请日：2009-12-17

Applicant: Sang-Jin BYEON ,  Beom-Ju Shin

Inventor： Sang-Jin BYEON ,  Beom-Ju Shin

IPC: G11C7/10

CPC classification number: G11C7/1048

Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

Abstract translation: 具有用于执行读或写操作的活动状态和除活动状态之外的非活动状态的所要求保护的发明的半导体存储器件包括数据输入/输出（I / O）线; 上拉锁存单元，用于在半导体存储器件处于非活动状态时拉起数据I / O线; 一个下拉锁存单元，用于在半导体存储器件处于非活动状态时下拉数据I / O线; 以及选择单元，用于选择性地驱动上拉锁存单元和下拉锁存单元中的一个。

公开(公告)号：US20130107980A1

公开(公告)日：2013-05-02

申请号：US13333863

申请日：2011-12-21

Applicant: Sang-Jin BYEON

Inventor： Sang-Jin BYEON

IPC: H04L27/00 ,  G06F12/00

CPC classification number: G11C5/02 ,  G06F12/00 ,  G11C7/10 ,  G11C7/222

Abstract: An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.

Abstract translation: 一种集成电路系统，包括：第一芯片，包括第一周期信号生成单元，被配置为产生第一周期信号，将从所述集成电路系统外部的电路施加的第一信号发送到第二芯片，并发送从所述第二周期信号发送的第二信号; 第二芯片包括被配置为产生第二周期信号的第二周期信号生成单元，所述第二周期信号生成单元被配置为生成与第一周期信号的周期之间的差相对应的代码 和第二周期信号，以及延迟单元，被配置为通过使用根据代码改变的延迟值来延迟第二信号。