公开(公告)号：US07047284B1

公开(公告)日：2006-05-16

申请号：US09713440

申请日：2000-11-15

申请人： Sanjive Agarwala ,  David A. Comisky ,  Charles L. Fuoco ,  Iain Robertson ,  David Hoyle ,  John Keay ,  Keith Balmer ,  Amarjit S. Bhandal ,  Christopher L. Mobley

发明人： Sanjive Agarwala ,  David A. Comisky ,  Charles L. Fuoco ,  Iain Robertson ,  David Hoyle ,  John Keay ,  Keith Balmer ,  Amarjit S. Bhandal ,  Christopher L. Mobley

IPC分类号： G06F15/177

CPC分类号： G06F13/37

摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

摘要翻译： 描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。 传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。 在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。 使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

公开(公告)号：US06868087B1

公开(公告)日：2005-03-15

申请号：US09713609

申请日：2000-11-15

申请人： Sanjive Agarwala ,  Iain Robertson ,  David A. Comisky ,  Charles L. Fuoco ,  Christopher L. Mobley

发明人： Sanjive Agarwala ,  Iain Robertson ,  David A. Comisky ,  Charles L. Fuoco ,  Christopher L. Mobley

IPC分类号： H04B7/212 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L47/6215 ,  H04L47/50

摘要： A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as a crucial part of the transfer controller. The request queue manager receives these data transfer request packets from plural transfer requests nodes. The request queue manager sorts transfer request packets by their priority level and stores them in the queue manager memory. The request queue manager processes dispatches transfer request packets to a free data channel based upon priority level and first-in-first-out within priority level.

摘要翻译： 具有集线器和端口的传输控制器被视为全局存储器映射的各个位置之间的通信集线器。 请求队列管理器作为传输控制器的关键部分。 请求队列管理器从多个传输请求节点接收这些数据传输请求分组。 请求队列管理器按照优先级排序传输请求数据包，并将其存储在队列管理器内存中。 请求队列管理器根据优先级和优先级别先进先出，处理将传送请求分组分派到空闲数据信道。

公开(公告)号：US06606686B1

公开(公告)日：2003-08-12

申请号：US09603645

申请日：2000-06-26

申请人： Sanjive Agarwala ,  Charles L. Fuoco ,  David A. Comisky ,  Timothy D. Anderson ,  Christopher L. Mobley

发明人： Sanjive Agarwala ,  Charles L. Fuoco ,  David A. Comisky ,  Timothy D. Anderson ,  Christopher L. Mobley

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/2515 ,  G06F2212/601

摘要： A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory. Control logic inhibits indication that tag bits matches address bits and that a cache entry is the least recently used for cache eviction if the corresponding way is configured as directly addressable memory. In an alternative embodiment, the memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of sets equal to 2M, where M is an integer, as cache memory and configuring remaining sets as directly addressable memory.

摘要翻译： 数据处理装置包括中央处理单元和可配置为高速缓冲存储器和可直接寻址存储器的存储器。 存储器可选择性地配置为高速缓冲存储器和可直接寻址的存储器，通过将选定数量的方式配置为直接可寻址存储器并且将剩余方式配置为高速缓冲存储器。 控制逻辑禁止标签位匹配地址位的指示，并且如果相应的方式被配置为直接可寻址存储器，则高速缓存条目是最近最少用于高速缓存驱逐的指示。 在替代实施例中，通过将等于2M的选定数量的集合（其中M是整数）配置为高速缓冲存储器并将剩余集合配置为直接可寻址存储器，可选地将存储器配置为高速缓存存储器和直接寻址存储器。

公开(公告)号：US06535958B1

公开(公告)日：2003-03-18

申请号：US09603637

申请日：2000-06-26

申请人： Charles L. Fuoco ,  Sanjive Agarwala ,  David A. Comisky ,  Timothy D. Anderson ,  Christopher L. Mobley

发明人： Charles L. Fuoco ,  Sanjive Agarwala ,  David A. Comisky ,  Timothy D. Anderson ,  Christopher L. Mobley

IPC分类号： G06F1300

CPC分类号： G06F12/0802 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0897

摘要： A data processing system having a central processing unit, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit includes a snoop unit generating snoop accesses to the at least one level one cache upon a direct memory access to the directly addressable memory. The snoop unit generates a write snoop access to both level one caches upon a direct memory access write to or a direct memory access read from the directly addressable memory. The level one cache also invalidates a cache entry upon a snoop hit and also writes back a dirty cache entry to the directly addressable memory. A level two memory is selectively configurable as part level two unified cache and part directly addressable memory.

摘要翻译： 具有中央处理单元，至少一个一级缓存，二级统一高速缓存，直接可寻址存储器和直接存储器访问单元的数据处理系统包括：窥探单元，生成窥探访问至少一级一级高速缓存 直接内存访问直接可寻址的内存。 窥探单元在从直接可寻址存储器读取的直接存储器访问写入或直接存储器访问时，产生对一级缓存的写入窥探访问。 一级缓存还会在侦听命中时使缓存条目无效，并将脏缓存条目写回到可直接寻址的存储器。 二级存储器可选择性地配置为部分二级统一缓存和部分直接可寻址存储器。

公开(公告)号：US06408345B1

公开(公告)日：2002-06-18

申请号：US09603331

申请日：2000-06-26

申请人： Charles L. Fuoco ,  Sanjive Agarwala ,  David A. Comisky ,  Christopher L. Mobley

发明人： Charles L. Fuoco ,  Sanjive Agarwala ,  David A. Comisky ,  Christopher L. Mobley

IPC分类号： G06F1328

CPC分类号： G06F12/0811 ,  G06F12/0848 ,  G06F12/0851 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/126 ,  G06F2212/2515 ,  G06F2212/601

摘要： This invention is a data processing system including a central processing unit executing program instructions to manipulate data, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit adapted for connection to an external memory. A superscalar memory transfer controller schedules plural non-interfering memory movements to and from the level two unified cache and the directly addressable memory each memory cycle in accordance with a predetermined priority of operation. The level one cache preferably includes a level one instruction cache and a level one data cache. The superscalar memory transfer controller is capable of scheduling plural cache tag memory read accesses and one cache tag memory write access in a single memory cycle. The superscalar memory transfer controller is capable of scheduling plural of cache access state machines in a single memory cycle. The superscalar memory transfer controller is capable of scheduling plural memory accesses to non-interfering memory banks of the level two unified cache in a single memory cycle.

摘要翻译： 本发明是一种数据处理系统，包括执行程序指令以操纵数据的中央处理单元，至少一级一级缓存，二级统一缓存，直接寻址存储器和适于连接外部存储器的直接存储器存取单元。 超标量存储器传送控制器根据预定的操作优先级，对来自二级统一高速缓存和直接可寻址存储器的多个非干扰存储器移动进行调度。 一级缓存优选地包括一级指令高速缓存和一级数据高速缓存。 超标量存储器传送控制器能够在单个存储器周期中调度多个缓存标签存储器读取访问和一个缓存标签存储器写访问。 超标量存储器传输控制器能够在单个存储器周期中调度多个高速缓存存取状态机。 超标量存储器传输控制器能够在单个存储器周期中调度对二级统一高速缓存的非干扰存储器组的多个存储器访问。

公开(公告)号：US06446241B1

公开(公告)日：2002-09-03

申请号：US09615119

申请日：2000-07-13

申请人： Christopher L. Mobley ,  Timothy D. Anderson ,  Charles L. Fuoco ,  Sanjive Agarwala

发明人： Christopher L. Mobley ,  Timothy D. Anderson ,  Charles L. Fuoco ,  Sanjive Agarwala

IPC分类号： G06F1750

CPC分类号： G11C29/56 ,  G06F12/0831 ,  G11C29/08

摘要： A method generates a list of allowed states in a cache design by applying each input transaction sequentially to all found legal cache states. If application of an input transaction to a current search cache results in a new cache state, then this new cache state is added to the list of legal cache states and to a list of search cache states. This is repeated for all input transactions and all such found legal cache states. At the same time a sequence of input transactions reaching each new cache state is formed. This new sequence is the sequence of input transactions for the prior cache state and the current input transaction. The method generates a series of test sequences from the list of allowed states and their corresponding sequence of input transactions which are applied to the control logic cache design and to a reference memory. If the response of the control logic cache design fails to match the response of the reference memory, then a design fault is detected.

摘要翻译： 方法通过将每个输入事务顺序地应用于所有找到的合法缓存状态来生成缓存设计中的允许状态列表。 如果将输入事务应用于当前搜索高速缓存导致新的高速缓存状态，则将该新的高速缓存状态添加到合法高速缓存状态列表和搜索高速缓存状态列表。 对于所有输入事务和所有这些发现的合法缓存状态，这是重复的。 同时形成到达每个新的高速缓存状态的一系列输入事务。 此新序列是先前缓存状态和当前输入事务的输入事务序列。 该方法从应用于控制逻辑高速缓存设计和参考存储器的允许状态列表及其相应的输入事务序列生成一系列测试序列。 如果控制逻辑高速缓存设计的响应不符合参考存储器的响应，则检测到设计故障。