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公开(公告)号：US09544133B2
公开(公告)日：2017-01-10
申请号：US12647459
申请日：2009-12-26
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译： 描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。 在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。 还描述了其它实施例。
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公开(公告)号：US20110158403A1
公开(公告)日：2011-06-30
申请号：US12647459
申请日：2009-12-26
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译： 描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。 在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。 还描述了其它实施例。
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公开(公告)号：US20150023500A1
公开(公告)日：2015-01-22
申请号：US14507427
申请日：2014-10-06
IPC分类号： H04L9/08
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译： 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。
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公开(公告)号：US08214414B2
公开(公告)日：2012-07-03
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F15/00
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。
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5.发明申请公开(公告)号：US20140229741A1
公开(公告)日：2014-08-14
申请号：US13993545
申请日：2011-12-30
CPC分类号： G06F21/72 , G06F21/60 , H04L9/0631 , H04L2209/122
摘要： A different set of polynomials may be selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
摘要翻译： 可以为加密和解密加速器选择不同的多项式集合。 也就是说，不同的多项式组用于加密和解密，每组被选择为使用较少的区域并为存储器加密引擎提供更多的功率。 这在一些实施例中是有利的，因为存储器读取操作通常比存储器写入更为关键和延迟敏感。
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公开(公告)号：US20100082718A1
公开(公告)日：2010-04-01
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F7/00
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。
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7.发明授权公开(公告)号：US08923510B2
公开(公告)日：2014-12-30
申请号：US11966658
申请日：2007-12-28
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译： 公开了高级加密标准（AES）加密和解密过程的实现。 在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。 对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。 最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。 在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。 在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。 将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。
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8.发明申请公开(公告)号：US20090172068A1
公开(公告)日：2009-07-02
申请号：US11966658
申请日：2007-12-28
IPC分类号： G06F7/38
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译： 公开了高级加密标准（AES）加密和解密过程的实现。 在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。 对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。 最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。 在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。 在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。 将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。
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公开(公告)号：US08855302B2
公开(公告)日：2014-10-07
申请号：US13165269
申请日：2011-06-21
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译： 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。
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公开(公告)号：US20120328097A1
公开(公告)日：2012-12-27
申请号：US13165269
申请日：2011-06-21
IPC分类号： H04L9/28
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译： 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。
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