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公开(公告)号：US4870406A
公开(公告)日：1989-09-26
申请号：US13842
申请日：1987-02-12
申请人： Satish Gupta , Leon Lumelsky , Robert L. Mansfield , Hector G. Romero, Jr. , Marc Segre , Alexander K. Spencer , Joe C. St. Clair , James D. Wagoner
发明人： Satish Gupta , Leon Lumelsky , Robert L. Mansfield , Hector G. Romero, Jr. , Marc Segre , Alexander K. Spencer , Joe C. St. Clair , James D. Wagoner
CPC分类号： G09G5/393
摘要： A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.
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公开(公告)号：US4648032A
公开(公告)日：1987-03-03
申请号：US701327
申请日：1985-02-13
CPC分类号： G09G5/001 , G06F3/153 , G09G2360/127 , G09G2360/18 , G09G5/393 , G09G5/395
摘要： A counter is used to concurrently refresh a video display and a memory associated with such video display. Address bits are output from the counter to the sync decode logic used to refresh the display as well as to multiplexing means connected to the associated memory. The multiplexing means has three pairs of inputs. The first pair of inputs comprises refresh addresses from the counter for refreshing the memory array. The second pair of inputs to the multiplexing means comprises memory update addresses for writing new information into the memory. A third pair of inputs to the multiplexing means performs two functions. The first function enables the multiplexing means to output either the update addresses or the refresh addresses depending on the state of such inputs. The second function of the third pair of inputs is to identify the output of said multiplexing means as either a row address or a column address to the associated memory. The apparatus and technique disclosed herein is especially pertinent when a "nibble mode" dynamic RAM is used as the memory.
摘要翻译： 计数器用于同时刷新视频显示器和与这种视频显示器相关联的存储器。 地址位从计数器输出到用于刷新显示器的同步解码逻辑以及连接到相关存储器的多路复用装置。 复用装置具有三对输入。 第一对输入包括用于刷新存储器阵列的来自计数器的刷新地址。 多路复用装置的第二对输入包括用于将新信息写入存储器的存储器更新地址。 多路复用装置的第三对输入执行两个功能。 第一功能使多路复用装置根据这种输入的状态输出更新地址或刷新地址。 第三对输入的第二功能是将所述多路复用装置的输出识别为相关存储器的行地址或列地址。 当使用“半字节模式”动态RAM作为存储器时，本文公开的装置和技术是特别相关的。
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公开(公告)号：US4401985A
公开(公告)日：1983-08-30
申请号：US313126
申请日：1981-10-20
CPC分类号： G09G5/222
摘要： A full page display device for a text processing system in which a text stream input by way of a keyboard is stored and displayed to the operator on a display device including a cathode ray tube, the electron beam of which is modulated and scanned in a series of horizontal traces to produce an image of the text line on the screen of the display device. The system comprises storage means which includes a plurality (four in a specific embodiment) of separate storage devices. In the specific embodiment, when the storage devices are accessed for display, one character is accessed simultaneously from the same location in each of the storage devices. The data is latched and coupled to a character generator to read out character dot pattern data which is latched and then interleaved with the data from other accessed character data by transferring the data one character at a time in parallel to a serializer. The data out of the serializer forms a serial bit stream which is coupled to the cathode ray tube to modulate the intensity of the beam in synchronism with the sweep to display the selected character data.
摘要翻译： 一种用于文本处理系统的全页显示装置，其中通过键盘输入的文本流被存储并显示给包括阴极射线管的显示装置的操作者，该阴极射线管的电子束被一系列地被调制和扫描 的水平轨迹，以在显示设备的屏幕上产生文本行的图像。 该系统包括存储装置，其包括分离的存储装置的多个（在具体实施例中为四个）。 在具体实施例中，当存储设备被访问以显示时，从每个存储设备中的相同位置同时访问一个字符。 数据被锁存并耦合到字符发生器，以通过与串行器并行地一次传送数据一个字符来读出被锁存的数据并随后与来自其他访问的字符数据的数据进行交织的字符点图形数据。 串行器之外的数据形成串联比特流，其连接到阴极射线管，以与扫描同步地调制波束的强度以显示所选择的字符数据。
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公开(公告)号：US06550013B1
公开(公告)日：2003-04-15
申请号：US09388952
申请日：1999-09-02
IPC分类号： G06F108
CPC分类号： G06F1/08
摘要： A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.
摘要翻译： 实现了存储器时钟发生器装置和方法。 从处理器时钟产生存储器时钟“开环”。 处理器时钟被选通并通过移位寄存器传播。 从移位寄存器中抽出的一组输出与多个控制信号一起被解码，并且以“或”逻辑进行解码，以生成可以以存储器时钟速率的预定倍数运行的时钟输出。 时钟输出可以具有存储器时钟周期与处理器时钟周期的多个比率中的一个。 控制信号选择比例。 时钟发生器可以异步启动，并且另外，发生器向具有与时钟发生器的开始具有预定时间关系的边沿的处理器输出信号。
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公开(公告)号：US4859815A
公开(公告)日：1989-08-22
申请号：US285921
申请日：1988-12-19
申请人： John W. Irwin , James D. Wagoner
发明人： John W. Irwin , James D. Wagoner
CPC分类号： H04L25/4906 , H04L1/0083
摘要： In a serial link in which it is necessary to occupy the link before and after transmission of a frame by sending a succession idle characters having alternating disparity effects, the disparity effect of the last character in the frame is compared with the disparity effect that would be produced by a disparity flip-flop, which has continued to step during frame transmission. If the disparity effect of these two characters match, no corrective action is required in order to resume the stream of idle characters. If the disparity effect of these characters differ, the disparity flip-flop is corrected before the stream of idle characters is resumed. Disclosed is hardware logic to accomplish this disparity control following transmission of frames in a transparent mode.
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