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公开(公告)号：US06903781B2
公开(公告)日：2005-06-07
申请号：US10184053
申请日：2002-06-28
CPC分类号： H04N5/45 , H04N9/641 , H04N21/426 , H04N21/4316 , H04N21/440263
摘要： A video signal processing apparatus comprises a sub-screen processing integrated circuit for subjecting a sub-screen video signal to scale-down processing to reduce its display region and output the sub-screen video signal, and a main-screen processing integrated circuit comprising: a switching circuit for receiving a main-screen video signal and the scaled-down sub-screen video signal which is outputted from the sub-screen processing integrated circuit, and selecting the main-screen video signal for a main-screen display region while selecting the sub-screen video signal for a sub-screen display region; an A/D conversion circuit for converting the video signal outputted from the switching circuit into a digital video signal; a digital signal processing circuit for digitally processing the digital video signal outputted from the A/D conversion circuit; and a D/A conversion circuit for converting the digitally-processed video signal into an analog video signal. Therefore, the main-screen video signal and the sub-screen video signal can be combined so that these signals are displayed on a single screen, and the circuit scale of the video signal processing apparatus can be minimized.
摘要翻译： 视频信号处理装置包括：子屏幕处理集成电路，用于对子屏幕视频信号进行缩小处理以减小其显示区域并输出子屏幕视频信号;以及主屏幕处理集成电路，包括： 用于接收主屏幕视频信号的切换电路和从子画面处理集成电路输出的按比例缩小的子画面视频信号，并且在选择主画面显示区域的同时选择主屏幕视频信号 用于子屏幕显示区域的子屏幕视频信号; A / D转换电路，用于将从开关电路输出的视频信号转换为数字视频信号; 数字信号处理电路，用于数字处理从A / D转换电路输出的数字视频信号; 以及用于将数字处理的视频信号转换为模拟视频信号的D / A转换电路。 因此，可以组合主屏幕视频信号和子屏幕视频信号，使得这些信号被显示在单个屏幕上，并且可以使视频信号处理设备的电路规模最小化。
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公开(公告)号：US20060146891A1
公开(公告)日：2006-07-06
申请号：US10541678
申请日：2004-11-19
IPC分类号： H04J3/06
CPC分类号： H03L7/07 , H03K5/13 , H03K5/1565 , H03L7/0814 , H04N5/126
摘要： In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells stepwisely to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. According to the semiconductor device of the present invention, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.
摘要翻译： 在本发明的半导体器件中，时钟不瞬时变化，但是通过逐步移动延迟单元，使其在最大N + 1 / M个时钟（N：不小于2的整数）上改变，以使之前的参考的相位状态 信号和本参考信号的相位状态彼此一致，从而精确地将时钟与参考信号同步，并且输出时钟的占空比保持恒定。 根据本发明的半导体器件，当输入参考信号与时钟不一致的信号时，可以防止时钟的占空比不连续，并且复位到该参考信号的上升沿。
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公开(公告)号：US07259599B2
公开(公告)日：2007-08-21
申请号：US10541678
申请日：2004-11-19
IPC分类号： H03L7/00
CPC分类号： H03L7/07 , H03K5/13 , H03K5/1565 , H03L7/0814 , H04N5/126
摘要： In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.
摘要翻译： 在本发明的半导体器件中，时钟不瞬时变化，但是通过逐步地移动延迟单元，在最大N + 1 / M个时钟（N：不小于2的整数）上改变时钟，以使相位 先前参考信号的状态和本参考信号的相位状态彼此一致，从而精确地将时钟与参考信号同步，并且输出时钟的占空比保持恒定。 利用该半导体器件，当输入参考信号与时钟不一致的信号时，可以防止时钟的占空比不连续，并且复位到该参考信号的上升沿。
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公开(公告)号：US07684649B2
公开(公告)日：2010-03-23
申请号：US11587204
申请日：2005-04-20
申请人： Hisao Kunitani , Satoru Tanigawa , Takashi Koizumi
发明人： Hisao Kunitani , Satoru Tanigawa , Takashi Koizumi
IPC分类号： G06K9/32
CPC分类号： G09G5/10 , G09G2360/16 , H04N5/08 , H04N5/14 , H04N5/20
摘要： To improve accuracy of determining the average brightness level and maximum and minimum levels of the brightness signals for the entire screen.There are included a differential operation circuit that detects and differentiates rise or breaking edges in horizontal and vertical synchronous signals of an input image signal, thereby outputting horizontal and vertical differential signals synchronized with the horizontal and vertical synchronous signals, respectively; a sample window circuit that detects the beginning and ending positions of horizontal and vertical intervals to produce sample window signals established in any desired vertical and horizontal positions on the screen in accordance with the horizontal and vertical differential signals; and a brightness signal output circuit that outputs sampled brightness signals when the sample window circuit is operative.
摘要翻译： 提高确定整个屏幕的亮度信号的平均亮度级别和最大和最小级别的精度。 包括差分运算电路，其检测和区分输入图像信号的水平和垂直同步信号中的上升沿或断裂边缘，从而分别输出与水平和垂直同步信号同步的水平和垂直差分信号; 样本窗口电路，其检测水平和垂直间隔的开始和结束位置，以根据水平和垂直差分信号产生在屏幕上的任何期望的垂直和水平位置中建立的样本窗口信号; 以及亮度信号输出电路，其在采样窗电路工作时输出采样的亮度信号。
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5.发明授权Video signal processing apparatus which generates plural clocks and performing video signal processing using the plural clocks 失效视频信号处理装置，其生成多个时钟并使用多个时钟执行视频信号处理公开(公告)号：US07683972B2
公开(公告)日：2010-03-23
申请号：US11357209
申请日：2006-02-21
申请人： Satoru Tanigawa
发明人： Satoru Tanigawa
摘要： A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.
摘要翻译： 视频信号处理装置设置有用于产生与输入信号同步的第一时钟的第一时钟产生电路; 第二时钟产生电路，用于接收设定值作为输出频率的参考，将每个参考时钟的设定值相加，根据累积值提取数据，将数据转换为模拟信号，减少量化噪声，并乘法 模拟信号，从而获得第二时钟; 以及时钟切换电路，用于通过使用由第一时钟产生的同步信号来产生切换到第二时钟的同步信号; 并且使用根据像素显示器的分辨率生成的第二时钟来执行视频信号处理。
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6.发明授权Video signal processor and video signal processing method which interpolate a video signal using an interpolation factor based on phase information of a selected clock 有权视频信号处理器和视频信号处理方法，其使用基于所选时钟的相位信息的内插因子来内插视频信号公开(公告)号：US07250981B2
公开(公告)日：2007-07-31
申请号：US10764439
申请日：2004-01-27
申请人： Satoru Tanigawa
发明人： Satoru Tanigawa
CPC分类号： H04N7/0135 , H03L7/0812 , H04N7/0105
摘要： A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a first clock signal is processed using a second clock signal, this video signal processor does not utilize as the second clock signal, a clock signal that is in phase with a reference signal but a clock signal that is employed in a later stage signal processor, and interpolates the video data signal by an interpolation circuit so as to make the signal in phase with the reference signal.
摘要翻译： 可以防止时钟的一个周期的长度被缩短并且可以输出与参考信号同相的视频信号的视频信号处理器和视频信号处理方法。 当使用第二时钟信号处理已经使用第一时钟信号处理的视频数据信号时，该视频信号处理器不利用与参考信号同时相位的时钟信号作为第二时钟信号， 用于后级信号处理器，并通过内插电路内插视频数据信号，使信号与参考信号同相。
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7.发明申请NOISE DETECTION METHOD AND IMAGE PROCESSING METHOD USING THE NOISE DETECTION METHOD 审中-公开噪声检测方法和使用噪声检测方法的图像处理方法公开(公告)号：US20100277647A1
公开(公告)日：2010-11-04
申请号：US12808637
申请日：2009-01-29
申请人： Satoru Tanigawa
发明人： Satoru Tanigawa
CPC分类号： H04N5/21 , H04N7/0115
摘要： An image processing method includes a difference extraction step (103) of outputting a frame difference signal from an input image signal and from an image signal that has been frame-delayed so that a base value of noise of the film image is acquired from a portion of the film image of a 2-3 pull-down scheme where a signal that is identical every five fields, an integration step (107) of accumulating output signals of the difference extraction step, a detection step (106) that a difference of the entire frames is small based on the output signal of the difference extraction step, and an acquisition step (108) of acquiring, as a noise amount, an integrated value of the frame in the integrated step at timing when it is detected in the detection step that a difference of the entire frames is small. With this, noise is detected by the image processing method. A noise reduction step (113) is carried out using a result of the detection of noise.
摘要翻译： 一种图像处理方法包括从输入图像信号输出帧差信号的差分提取步骤（103）和已被帧延迟的图像信号，从而获得胶片图像的噪声的基值 对每5场相同信号的2-3下拉方案的电影图像进行积分步骤（107），累积差分提取步骤的输出信号;检测步骤（106），其差异为 基于差分提取步骤的输出信号，整个帧较小，以及获取步骤（108），其在检测步骤中检测到的定时获取积分步骤中的帧的积分值作为噪声量 整个框架的差异很小。 由此，通过图像处理方法检测噪声。 使用噪声检测的结果来执行降噪步骤（113）。
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8.发明授权Motion detection device and method, luminance/chrominance signal separation device and method, noise reduction device and method, and video display device and method 有权运动检测装置和方法，亮度/色度信号分离装置和方法，降噪装置和方法以及视频显示装置和方法公开(公告)号：US07796783B2
公开(公告)日：2010-09-14
申请号：US12276842
申请日：2008-11-24
申请人： Satoru Tanigawa
发明人： Satoru Tanigawa
IPC分类号： G06K9/00
摘要： The motion detection device includes an oblique correlation detection section, a motion detection section and a motion determination section. The oblique correlation detection section detects a correlation in an oblique direction (oblique correlation) of a composite video signal. The motion detection section detects a motion amount based on an inter-frame difference of the composite video signal. The motion determination section determines the presence/absence of a motion in the composite video signal based on the motion amount detected by the motion detection section. The motion determination section determines the presence/absence of the motion considering the detection results of the oblique correlation by the oblique correlation detection section.
摘要翻译： 运动检测装置包括倾斜相关检测部，运动检测部和运动判定部。 倾斜相关检测部检测复合视频信号的倾斜方向（倾斜相关）的相关性。 运动检测部分基于复合视频信号的帧间差检测运动量。 运动判定部基于由运动检测部检测出的运动量来决定复合视频信号中的动作的有无。 考虑到倾斜相关检测部分的倾斜相关的检测结果，运动确定部分确定运动的存在/不存在。
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9.发明授权Contour correcting device, contour correcting method and video display device 有权轮廓校正装置，轮廓校正方法和视频显示装置公开(公告)号：US08774547B2
公开(公告)日：2014-07-08
申请号：US12529463
申请日：2008-09-11
申请人： Nobuko Fujita , Satoru Tanigawa
发明人： Nobuko Fujita , Satoru Tanigawa
CPC分类号： H04N5/208 , G06F3/1423 , G06T5/003 , G06T5/20 , G06T2207/10016 , G06T2207/20192 , G09G2320/02 , H04N1/4092
摘要： A contour correcting device which includes a plurality of delay elements which delay an input video signal, a pixel-selection-control-signal generation circuit, a pixel selection circuit which selects outputs of the plurality of delay elements in response to outputs of the pixel-selection-control-signal generation circuit, a high-pass filter operation circuit and an adder circuit which adds an operation result of the high-pass filter operation circuit to the input video signal. When the pixel selection circuit extracts a contour component in a boundary portion between a horizontal video effective period and a period other than the horizontal video effective period of the input video signal, the pixel selection circuit replaces pixel data in the period other than the horizontal video effective period among pixel data input to the high-pass filter operation circuit, with pixel data at an edge-point of the horizontal video effective period.
摘要翻译： 一种轮廓校正装置，其包括延迟输入视频信号的多个延迟元件，像素选择控制信号生成电路，响应于像素选择控制信号生成电路的输出而选择多个延迟元件的输出的像素选择电路， 选择控制信号生成电路，高通滤波器运算电路和加法电路，将高通滤波运算电路的运算结果与输入图像信号相加。 当像素选择电路在水平视频有效期间和除了输入视频信号的水平视频有效期之外的周期之间的边界部分中提取轮廓分量时，像素选择电路在水平视频以外的周期中替换像素数据 输入到高通滤波器运算电路的像素数据中的有效期间，在水平视频有效期的边缘点处具有像素数据。
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公开(公告)号：US20060187349A1
公开(公告)日：2006-08-24
申请号：US11357209
申请日：2006-02-21
申请人： Satoru Tanigawa
发明人： Satoru Tanigawa
摘要： A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.
摘要翻译： 视频信号处理装置设置有用于产生与输入信号同步的第一时钟的第一时钟产生电路; 第二时钟产生电路，用于接收设定值作为输出频率的参考，将每个参考时钟的设定值相加，根据累积值提取数据，将数据转换为模拟信号，减少量化噪声，并乘法 模拟信号，从而获得第二时钟; 以及时钟切换电路，用于通过使用由第一时钟产生的同步信号来产生切换到第二时钟的同步信号; 并且使用根据像素显示器的分辨率生成的第二时钟来执行视频信号处理。
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