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1.发明授权Method of manufacturing a photo mask and method of manufacturing a semiconductor device 有权制造光掩模的方法和制造半导体器件的方法公开(公告)号：US07090949B2
公开(公告)日：2006-08-15
申请号：US10724738
申请日：2003-12-02
申请人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
发明人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
IPC分类号： G01F9/00
摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.
摘要翻译： 公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应 对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取 基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸 预定条件。
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2.发明授权Method of creating predictive model, method of managing process steps, method of manufacturing semiconductor device, method of manufacturing photo mask, and computer program product 有权创建预测模型的方法，管理工艺步骤的方法，制造半导体器件的方法，制造光罩的方法以及计算机程序产品公开(公告)号：US07473495B2
公开(公告)日：2009-01-06
申请号：US10927218
申请日：2004-08-27
申请人： Satoshi Tanaka , Soichi Inoue , Koji Hashimoto , Shigeru Hasebe
发明人： Satoshi Tanaka , Soichi Inoue , Koji Hashimoto , Shigeru Hasebe
IPC分类号： G03F9/00
CPC分类号： G03F1/36 , G06F17/5068
摘要： A method of creating a predictive model of a process proximity effect comprises: preparing a predictive model of a process proximity effect including a non-determined parameter; and determining the non-determined parameter, the method comprises: preparing a pattern group for modeling, the pattern group comprising a plurality of repetition patterns, the plurality of repetition patterns being obtained by changing a first and second dimensions of a repetition pattern which repeats a basic pattern, the first dimension defining the basic pattern, and the second dimension defining repetition of the basic pattern; selecting a predetermined repetition pattern from the pattern group for modeling, the basic pattern of the predetermined repetition pattern corresponding to a pattern which is to be formed on a wafer and has a predetermined dimension; and determining the non-determined parameter in the predictive model based on the predetermined repetition pattern and the pattern having the predetermined dimension.
摘要翻译： 一种创建过程接近效应的预测模型的方法包括：准备包括非确定参数的过程接近效应的预测模型; 并且确定所述未确定的参数，所述方法包括：准备用于建模的图案组，所述图案组包括多个重复图案，所述多个重复图案是通过改变重复图案的重复图案的第一和第二维度而获得的 基本图案，定义基本图案的第一维度和定义基本图案重复的第二维度; 从所述图案组中选择预定的重复图案以进行建模，所述预定重复图案的基本图案与将要形成在晶片上并且具有预定尺寸的图案相对应; 以及基于预定重复图案和具有预定尺寸的图案来确定预测模型中的未确定参数。
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3.发明申请Method of creating predictive model, method of managing process steps, method of manufacturing semiconductor device, method of manufacturing photo mask, and computer program product 有权创建预测模型的方法，管理工艺步骤的方法，制造半导体器件的方法，制造光罩的方法以及计算机程序产品公开(公告)号：US20050089768A1
公开(公告)日：2005-04-28
申请号：US10927218
申请日：2004-08-27
申请人： Satoshi Tanaka , Soichi Inoue , Koji Hashimoto , Shigeru Hasebe
发明人： Satoshi Tanaka , Soichi Inoue , Koji Hashimoto , Shigeru Hasebe
CPC分类号： G03F1/36 , G06F17/5068
摘要： A method of creating a predictive model of a process proximity effect comprises: preparing a predictive model of a process proximity effect including a non-determined parameter; and determining the non-determined parameter, the method comprises: preparing a pattern group for modeling, the pattern group comprising a plurality of repetition patterns, the plurality of repetition patterns being obtained by changing a first and second dimensions of a repetition pattern which repeats a basic pattern, the first dimension defining the basic pattern, and the second dimension defining repetition of the basic pattern; selecting a predetermined repetition pattern from the pattern group for modeling, the basic pattern of the predetermined repetition pattern corresponding to a pattern which is to be formed on a wafer and has a predetermined dimension; and determining the non-determined parameter in the predictive model based on the predetermined repetition pattern and the pattern having the predetermined dimension.
摘要翻译： 一种创建过程接近效应的预测模型的方法包括：准备包括非确定参数的过程接近效应的预测模型; 并且确定所述未确定的参数，所述方法包括：准备用于建模的图案组，所述图案组包括多个重复图案，所述多个重复图案是通过改变重复图案的重复图案的第一和第二维度而获得的 基本图案，定义基本图案的第一维度和定义基本图案重复的第二维度; 从所述图案组中选择预定的重复图案以进行建模，所述预定重复图案的基本图案与将要形成在晶片上并且具有预定尺寸的图案相对应; 以及基于预定重复图案和具有预定尺寸的图案来确定预测模型中的未确定参数。
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4.发明申请Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 失效掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法公开(公告)号：US20050250022A1
公开(公告)日：2005-11-10
申请号：US11068896
申请日：2005-03-02
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。
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5.发明申请Method of setting process parameter and method of setting process parameter and/or design rule 有权设置过程参数的方法和设置过程参数和/或设计规则的方法公开(公告)号：US20050177811A1
公开(公告)日：2005-08-11
申请号：US11105431
申请日：2005-04-14
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。
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6.发明授权Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 有权掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法公开(公告)号：US08142961B2
公开(公告)日：2012-03-27
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。
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7.发明申请MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权掩模图像校正方法，掩模图案检查方法，照相胶片制造方法和半导体器件制造方法公开(公告)号：US20100159709A1
公开(公告)日：2010-06-24
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： H01L21/302 , G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。
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8.发明授权Method of setting process parameter and method of setting process parameter and/or design rule 有权设置过程参数的方法和设置过程参数和/或设计规则的方法公开(公告)号：US07120882B2
公开(公告)日：2006-10-10
申请号：US11105431
申请日：2005-04-14
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。
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9.发明授权Method of setting process parameter and method of setting process parameter and/or design rule 有权设置过程参数的方法和设置过程参数和/或设计规则的方法公开(公告)号：US07181707B2
公开(公告)日：2007-02-20
申请号：US10385628
申请日：2003-03-12
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。
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10.发明授权Phase shifting mask comprising a multilayer structure and method of forming a pattern using the same 失效相移掩模，其包括多层结构和使用其形成图案的方法
公开(公告)号：US5514499A
公开(公告)日：1996-05-07
申请号：US249038
申请日：1994-05-25
申请人： Takayuki Iwamatsu , Kenji Kawano , Hideya Miyazaki , Shinichi Ito , Soichi Inoue , Hiroyuki Sato , Satoshi Tanaka , Koji Hashimoto
发明人： Takayuki Iwamatsu , Kenji Kawano , Hideya Miyazaki , Shinichi Ito , Soichi Inoue , Hiroyuki Sato , Satoshi Tanaka , Koji Hashimoto
摘要： A reflection phase shifting mask used to expose a pattern by forming reflected light having a phase difference upon reflection of light, includes a substrate for reflecting exposure light, a phase shifting layer formed on a portion on the substrate, and a light transmitting medium formed on the substrate and the phase shifting layer, wherein the thickness of the phase shifting layer is set such that the phase difference between light reflected by the substrate and light reflected by the phase shifting layer becomes 180.degree..
摘要翻译： 用于通过在光反射时形成具有相位差的反射光来曝光图案的反射相移掩模包括反射曝光光的基板，形成在基板上的部分上的相移层和形成在基板上的光传输介质 基板和相移层，其中相移层的厚度被设定为使得由基板反射的光与由相移层反射的光之间的相位差成为180度。
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