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    METHOD AND SYSTEM FOR RELIABLE CFO AND STO ESTIMATION IN THE PRESENCE OF TUNER INDUCED IMPAIRMENT
    1.
    发明申请
    METHOD AND SYSTEM FOR RELIABLE CFO AND STO ESTIMATION IN THE PRESENCE OF TUNER INDUCED IMPAIRMENT 有权
    调节器诱导损伤存在的可靠的CFO和STO估计方法与系统

    公开(公告)号：US20120250750A1

    公开(公告)日：2012-10-04

    申请号：US13435945

    申请日：2012-03-30

    申请人： Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S. Harish Krishnan ,  Gururaj Padaki

    发明人： Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S. Harish Krishnan ,  Gururaj Padaki

    IPC分类号： H04B17/00

    CPC分类号： H04L27/0014 ,  H04L2027/003 ,  H04L2027/0065

    摘要： A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

    摘要翻译： 用于降低用于频谱形状的多通信标准的输入信号的载波频偏（CFO）和符号定时偏移（STO）的实现复杂度的系统和方法。 该系统通过用移位器替换乘法器来实现。 该系统包括CFO估计块，STO估计块和提取输入信号的较低频带边沿和上边带边缘的频带提取块。 STO估计块包括（i）计算采样定时误差值的采样误差产生块，以及（ii）估计与采样定时误差值对应的频率误差和相位误差的锁相环块。 CFO估计块包括（i）产生载波偏移误差值的载波偏移误差产生块，和（ii）用于执行滤波操作的泄漏平均块。

    Method and system for reliable CFO and STO estimation in the presence of tuner induced impairment
    2.
    发明授权
    Method and system for reliable CFO and STO estimation in the presence of tuner induced impairment 有权
    在调谐器诱发损伤的情况下可靠的CFO和STO估计的方法和系统

    公开(公告)号：US08611471B2

    公开(公告)日：2013-12-17

    申请号：US13435945

    申请日：2012-03-30

    申请人： Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S Harish Krishnan ,  Gururaj Padaki

    发明人： Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S Harish Krishnan ,  Gururaj Padaki

    IPC分类号： H04L27/00

    CPC分类号： H04L27/0014 ,  H04L2027/003 ,  H04L2027/0065

    摘要： A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

    摘要翻译： 用于降低用于频谱形状的多通信标准的输入信号的载波频偏（CFO）和符号定时偏移（STO）的实现复杂度的系统和方法。 该系统通过用移位器替换乘法器来实现。 该系统包括CFO估计块，STO估计块和提取输入信号的较低频带边沿和上边带边缘的频带提取块。 STO估计块包括（i）计算采样定时误差值的采样误差产生块，以及（ii）估计与采样定时误差值对应的频率误差和相位误差的锁相环块。 CFO估计块包括（i）产生载波偏移误差值的载波偏移误差产生块，和（ii）用于执行滤波操作的泄漏平均块。

    DIGITAL DOWNCONVERSION AND FAST CHANNEL SELECTION OF NARROWBAND SIGNALS USING A WIDE BAND RF TUNER
    3.
    发明申请
    DIGITAL DOWNCONVERSION AND FAST CHANNEL SELECTION OF NARROWBAND SIGNALS USING A WIDE BAND RF TUNER 有权
    使用宽带射频调谐器的数字眩光和快速通道选择窄带信号

    公开(公告)号：US20120269300A1

    公开(公告)日：2012-10-25

    申请号：US13447089

    申请日：2012-04-13

    申请人： Subramanian Harish Krishnan ,  Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  Gururaj Padaki ,  Santosh Billava

    发明人： Subramanian Harish Krishnan ,  Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  Gururaj Padaki ,  Santosh Billava

    IPC分类号： H04B1/10

    CPC分类号： H04B1/001

    摘要： A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

    摘要翻译： 提供了一种宽带接收机，通过对数字域中的输入信号进行滤波来选择和解调具有单扫描频谱感测的输入信号，以实现提高的选择性和灵敏度。 输入信号包括一个或多个窄带射频（RF）信号。 宽带接收机包括将一个或多个窄带RF信号下变换成一个或多个IF信号的宽带调谐器。 模数转换器（ADC）将一个或多个IF信号转换成一个或多个数字信号。 滤波器拒绝来自一个或多个数字信号的带外信号以实现改进的选择性。 数控振荡器（NCO）基于从频谱选择控制单元获得的相位值，从数字信号中选择至少一个窄带数字信号。 解调器解调窄带数字信号以获得解调的数字信号。

    Digital filter implementation for exploiting statistical properties of signal and coefficients
    4.
    发明授权
    Digital filter implementation for exploiting statistical properties of signal and coefficients 有权
    数字滤波器实现，用于利用信号和系数的统计特性

    公开(公告)号：US08812569B2

    公开(公告)日：2014-08-19

    申请号：US13462116

    申请日：2012-05-02

    申请人： Parag Naik ,  Anindya Saha ,  Gururaj Padaki ,  Subrahmanya Kondageri Shankaraiah ,  Saurabh Mishra

    发明人： Parag Naik ,  Anindya Saha ,  Gururaj Padaki ,  Subrahmanya Kondageri Shankaraiah ,  Saurabh Mishra

    IPC分类号： G06F17/10 ,  G06F7/38

    CPC分类号： H03H21/0012 ,  H03H2021/007 ,  H03H2021/0072 ,  H03H2218/10

    摘要： A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

    摘要翻译： 提供一种实现数字滤波器的方法。 该方法包括（a）通过测量输入数据样本的前导零或一个之间的距离以及输入数据样本的尾随零来确定输入信号的输入数据样本的位宽。 输入数据样本是通过以预定义的时间间隔对输入信号进行采样而获得的，（b）基于输入数据样本的位宽的第一概率分布函数（PDF））获得具有可变位宽的位宽乘数 ，（c）基于输入数据样本的位宽和滤波器系数的位宽分配输入数据样本和滤波器系数到位宽乘法器的一个位宽倍数，以及（d） 在一个位宽乘数上执行乘法和累加（MAC）运算的乘法运算，以产生数字滤波器的输出。

    System and Method to Reduce Channel Acquisition and Channel Switch Timings in Communication Receivers
    5.
    发明申请
    System and Method to Reduce Channel Acquisition and Channel Switch Timings in Communication Receivers 有权
    减少通信接收机中信道采集和信道切换时序的系统和方法

    公开(公告)号：US20120249887A1

    公开(公告)日：2012-10-04

    申请号：US13433819

    申请日：2012-03-29

    申请人： Sunil HR ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

    发明人： Sunil HR ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

    IPC分类号： H04N5/455

    CPC分类号： H04N21/4384 ,  H04N5/455 ,  H04N5/46 ,  H04N5/50 ,  H04N21/42676 ,  H04N21/4345

    摘要： A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

    摘要翻译： 提供了一种用于多个广播电视频道之间更快的频道切换时间的电视（TV）接收机，具有用于多个解调标准的整个解调周期中的延迟降低。 电视接收机包括从广播系统接收广播电视频道的调谐器，执行调谐操作，并且在频道扫描操作期间为每个广播电视频道设置期望的频率。 解调器解调每个广播电视频道，并且在频道扫描操作期间获取每个广播电视频道的一个或多个采集频道参数。 应用处理器经由低吞吐量接口耦合到解调器。 当信道状态从第一状态切换到第二状态时，应用处理器对解调器上的存储器映射寄存器执行读取操作和采集通道参数的写入操作。

    System and method to reduce channel acquisition and channel switch timings in communication receivers
    6.
    发明授权
    System and method to reduce channel acquisition and channel switch timings in communication receivers 有权
    减少通信接收机中信道采集和信道切换时序的系统和方法

    公开(公告)号：US08605225B2

    公开(公告)日：2013-12-10

    申请号：US13433819

    申请日：2012-03-29

    申请人： Sunil Hosur Ramesh ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

    发明人： Sunil Hosur Ramesh ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

    IPC分类号： H04N5/50

    CPC分类号： H04N21/4384 ,  H04N5/455 ,  H04N5/46 ,  H04N5/50 ,  H04N21/42676 ,  H04N21/4345

    摘要： A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

    摘要翻译： 提供了一种用于多个广播电视频道之间更快的频道切换时间的电视（TV）接收机，具有用于多个解调标准的整个解调周期中的延迟降低。 电视接收机包括从广播系统接收广播电视频道的调谐器，执行调谐操作，并且在频道扫描操作期间为每个广播电视频道设置期望的频率。 解调器解调每个广播电视频道，并且在频道扫描操作期间获取每个广播电视频道的一个或多个采集频道参数。 应用处理器经由低吞吐量接口耦合到解调器。 当信道状态从第一状态切换到第二状态时，应用处理器对解调器上的存储器映射寄存器执行读取操作和采集通道参数的写入操作。

    Index generation scheme for prime factor algorithm based mixed radix discrete fourier transform (DFT)
    7.
    发明授权
    Index generation scheme for prime factor algorithm based mixed radix discrete fourier transform (DFT) 有权
    基于素数算法的混合基数离散傅里叶变换（DFT）的索引生成方案

    公开(公告)号：US08832171B2

    公开(公告)日：2014-09-09

    申请号：US13435073

    申请日：2012-03-30

    申请人： Gururaj Padaki ,  Saurabh Mishra ,  Suman Sanisetty

    发明人： Gururaj Padaki ,  Saurabh Mishra ,  Suman Sanisetty

    IPC分类号： G06F17/14

    CPC分类号： G06F17/144

    摘要： In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ‘N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.

    摘要翻译： 在一个实施例中，处理器执行为没有查找表的Prime Factor Algorithm（PFA）离散傅立叶变换（DFT）生成流水线数据读索引和数据写入索引的方法。 处理器适于将“N”点PFA DFT分解为一个或多个互相因素和零个或多个非素因子，计算第i行（Xi0）的第0列索引，当Xi0的值计算IndCor 等于0，当行号（i）不等于零时，计算Xij，生成数据读取索引，对Lk点执行DFT内核计算互相素数因子和非素数因子，并生成数据写入索引 相互关联的因素和非主要因素。 Xij表示2D输入缓冲区的第i行和第j列，并且可以从2D输入缓冲区中选择一个线性索引。

    Zero overhead block floating point implementation in CPU's
    8.
    发明授权
    Zero overhead block floating point implementation in CPU's 有权
    CPU中的零开销块浮点实现

    公开(公告)号：US08788549B2

    公开(公告)日：2014-07-22

    申请号：US13461902

    申请日：2012-05-02

    申请人： Gururaj Padaki ,  Anindya Saha ,  Parag Naik ,  Vishwakumara Kayargadde ,  Sunil Hr

    发明人： Gururaj Padaki ,  Anindya Saha ,  Parag Naik ,  Vishwakumara Kayargadde ,  Sunil Hr

    IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/483

    CPC分类号： G06F7/483

    摘要： A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

    摘要翻译： 提供了一种用于通过检测中央处理单元中的输入信号的动态范围来计算块浮点缩放因子的系统，而没有额外的开销周期。 该系统包括动态范围监测单元，其通过窥探输出写入数据和输入信号的输入存储器读取数据来检测输入信号的动态范围。 动态范围监视单元包括运行的最大计数单元，其存储前导零和前导零的计数的最小值，以及存储尾随零计数的最小值的运行最小计数。 基于前导零和前导零的计数的最小值和尾随零的计数来检测动态范围。 该系统还包括一个缩放因子计算模块，它根据动态范围计算块浮点（BFP）缩放因子。

    Index Generation Scheme for Prime Factor Algorithm Based Mixed Radix Discrete Fourier Transform (DFT)
    10.
    发明申请
    Index Generation Scheme for Prime Factor Algorithm Based Mixed Radix Discrete Fourier Transform (DFT) 有权
    基于优化因子算法的混合偏离离散傅里叶变换（DFT）的索引生成方案

    公开(公告)号：US20120254274A1

    公开(公告)日：2012-10-04

    申请号：US13435073

    申请日：2012-03-30

    申请人： Gururaj Padaki ,  Saurabh Mishra ,  Suman Sanisetty

    发明人： Gururaj Padaki ,  Saurabh Mishra ,  Suman Sanisetty

    IPC分类号： G06F17/14

    CPC分类号： G06F17/144

    摘要： In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ‘N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.

    摘要翻译： 在一个实施例中，处理器执行为没有查找表的Prime Factor Algorithm（PFA）离散傅立叶变换（DFT）生成流水线数据读索引和数据写入索引的方法。 处理器适于将N点PFA DFT分解成一个或多个互相因子和零个或多个非素因子，计算第i行（Xi0）的第0列索引，当Xi0的值等于零时计算IndCor 并且当行号（i）不等于零时，计算Xij，生成数据读取索引，对Lk点执行DFT内核计算的互相素因子和非素数因子，并生成数据写入索引 互惠因素和非素因素。 Xij表示2D输入缓冲区的第i行和第j列，并且可以从2D输入缓冲区中选择一个线性索引。