公开(公告)号：US20170311440A1

公开(公告)日：2017-10-26

申请号：US15491727

申请日：2017-04-19

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Travis C. Mallett ,  Ben M. Armstrong ,  Forrest A. Rahrer

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/0265 ,  H05K1/0206 ,  H05K3/429 ,  H05K2201/09572

Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

公开(公告)号：US11564309B2

公开(公告)日：2023-01-24

申请号：US16704540

申请日：2019-12-05

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Travis C. Mallett ,  Ben M. Armstrong ,  Forrest A. Rahrer

IPC: H05K1/02 ,  H05K3/42

Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

公开(公告)号：US10537016B2

公开(公告)日：2020-01-14

申请号：US15491727

申请日：2017-04-19

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Travis C. Mallett ,  Ben M. Armstrong ,  Forrest A. Rahrer

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40

Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.