公开(公告)号：US20190254175A1

公开(公告)日：2019-08-15

申请号：US16335027

申请日：2017-10-13

申请人： Hella GmbH & Co. KGaA

发明人： Ralf Stanzmann

IPC分类号： H05K3/40 ,  H05K1/14 ,  H05K1/11 ,  H05K1/09 ,  H05K3/00 ,  H05K3/36 ,  H05K3/46 ,  H05K3/42

CPC分类号： H05K3/4038 ,  H05K1/09 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/36 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/041 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/061

摘要： A printed circuit board is provided with multiple electrically conductive layers which are separated from each other by electrically non-conductive layers. At least one electrically conductive outer layer and multiple electrically conductive intermediate layers are provided. At least one electrically conductive through-connection is provided between an electrically conductive outer layer and an electrically conductive intermediate layer. The printed circuit board consists of at least one first multi layer PCB and one second multilayer PCB. The first multilayer PCB is formed from multiple electrically conductive layers and multiple electrically non-conductive layers, and the second multilayer PCB has at least one electrically conductive layer and at least one electrically non-conductive layer. The multilayer PCBs are connected to each other. The electrically conductive through-connection between a first electrically conductive outer layer and a second electrically conductive outer layer is formed from multilayer PCBs.

公开(公告)号：US20190208645A1

公开(公告)日：2019-07-04

申请号：US16298896

申请日：2019-03-11

申请人： Sanmina Corporation

发明人： Shinichi Iketani ,  Dale Kersten

IPC分类号： H05K3/42 ,  H05K1/11

CPC分类号： H05K3/429 ,  H05K1/116 ,  H05K3/0094 ,  Y10T29/49165

摘要： Laminate structures including hole plugs, and methods for forming a hole plug in a laminate structure are provided. A laminate structure may be formed with at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. A blind hole may be formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the blind hole including a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). Via fill ink may be disposed in the blind hole, and the via fill ink may be dried and/or cured to form a hole plug.

公开(公告)号：US20190171271A1

公开(公告)日：2019-06-06

申请号：US16267310

申请日：2019-02-04

申请人： Super Micro Computer, Inc.

发明人： Manhtien Phan

IPC分类号： G06F1/30 ,  H04Q1/06 ,  H05K3/42 ,  G06F1/18 ,  H02B1/20 ,  H04Q1/14

CPC分类号： G06F1/30 ,  G06F1/189 ,  H02B1/202 ,  H04Q1/06 ,  H04Q1/14 ,  H05K3/429

摘要： Techniques pertaining to powering multiple platforms with a minimum impact on air passage in a predefined environment are disclosed. Instead of connecting each of the platforms in a chassis to a power supply therein, embodiments of the present invention uses what is referred to as cascading powering to power all platforms within minimum cable delivery. According to one embodiment of the present invention, a motherboard is disposed between two power supply units that are used to power the motherboard. The motherboard has power connectors located towards or near the power supply units so that only short cables are needed to power the platform.

公开(公告)号：US20190037709A1

公开(公告)日：2019-01-31

申请号：US15662959

申请日：2017-07-28

申请人： International Business Machines Corporation

发明人： Gerald K. Bartley ,  Darryl J. Becker ,  Matthew S. Doyle ,  Mark J. Jeanson

IPC分类号： H05K3/40 ,  H05K1/11 ,  H05K3/42 ,  H05K3/12 ,  H05K3/32

CPC分类号： H05K3/4046 ,  H05K1/113 ,  H05K3/1266 ,  H05K3/323 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/083 ,  H05K2203/0713 ,  H05K2203/104

摘要： A method and apparatus are provided for implementing customized printed circuit board (PCB) via creation through use of magnetic capture pads. At least one magnetic capture pad is rendered before aqueous seed and plate processing in the PCB manufacture. The magnetic capture pad selectively provides seed material rendering copper in at least one selected region of the via.

公开(公告)号：US20180332719A1

公开(公告)日：2018-11-15

申请号：US15593610

申请日：2017-05-12

申请人： International Business Machines Corporation

发明人： Matthew S. DOYLE ,  Joseph KUCZYNSKI ,  Phillip V. MANN ,  Kevin M. O'CONNELL

IPC分类号： H05K3/42 ,  H05K3/00 ,  H05K3/22

CPC分类号： H05K3/429 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/421 ,  H05K2201/0254 ,  H05K2201/09509 ,  H05K2201/09563

摘要： A method and associated apparatus are disclosed for forming a conductive via that extends partly through a multi-layer assembly, wherein the method comprises forming a cavity from a surface of the multi-layer assembly to a first depth. The cavity extends through a plurality of layers of the multi-layer assembly. The plurality of layers comprises a healing layer comprising a plurality of microcapsules. Forming the cavity ruptures some of the plurality of microcapsules to release encapsulated material into the cavity. The released encapsulated material defines a second depth from the surface, the second depth being closer to the surface than the first depth. The method further comprises depositing conductive material within the cavity to form the conductive via that extends to the second depth.

公开(公告)号：US20180324958A1

公开(公告)日：2018-11-08

申请号：US15773772

申请日：2016-11-23

申请人： RICHVIEW ELECTRONICS CO., LTD.

发明人： Siping Bai ,  Xianglan Wu ,  Zhijian Wang ,  Zhigang Yang ,  Jinqiang Zhang

IPC分类号： H05K3/42 ,  C23C14/48 ,  H05K1/11

CPC分类号： H05K3/429 ,  C23C14/48 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/096 ,  H05K2203/092

摘要： A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

公开(公告)号：US20180310418A1

公开(公告)日：2018-10-25

申请号：US16019452

申请日：2018-06-26

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Stig KALLMAN ,  Tomas BERGSTEN

IPC分类号： H05K3/42 ,  C25D5/02 ,  H05K1/09 ,  H05K1/11

CPC分类号： H05K3/429 ,  C25D5/02 ,  C25D5/022 ,  H05K1/092 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09645 ,  H05K2203/0713

摘要： The embodiments herein relate to an apparatus and medium for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The apparatus and medium implement a step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.

公开(公告)号：US20180279473A1

公开(公告)日：2018-09-27

申请号：US15928042

申请日：2018-03-21

申请人： SANMINA CORPORATION

发明人： Shinichi Iketani

IPC分类号： H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/06

CPC分类号： H05K1/115 ,  H05K3/0047 ,  H05K3/02 ,  H05K3/06 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2203/0207 ,  H05K2203/061 ,  H05K2203/0723

摘要： A multilayer PCB having may include a first sub-composite core having a first core structure sandwiched between a first conductive layer and a second conductive layer, the first core structure including one or more dielectric and conductive layers. A first via hole extends at least partially through the first core structure, wherein an inner surface of the first via hole is plated with a conductive material along a first via segment electrically coupling the first conductive layer to an internal layer or trace within the first core structure. A second via segment extending between the second conductive layer and the internal layer or trace is devoid of the conductive material such that the first via hole is substantially stub free. A first dielectric layer is coupled to the second conductive layer. A second sub-composite core coupled to the first dielectric layer.

公开(公告)号：US20180272573A1

公开(公告)日：2018-09-27

申请号：US15465073

申请日：2017-03-21

申请人： International Business Machines Corporation

发明人： Sarah K. Czaplewski ,  Joseph F. Doman ,  Joseph Kuczynski

IPC分类号： B29C41/02 ,  B29C41/00 ,  B29C41/46 ,  B29C41/42 ,  B29C41/50 ,  H05K3/00 ,  H05K1/11

CPC分类号： B29C41/02 ,  B29C41/003 ,  B29C41/42 ,  B29C41/46 ,  B29C41/50 ,  B29K2075/00 ,  B29K2083/00 ,  B29L2031/757 ,  H05K3/429 ,  H05K2203/16

摘要： Circuit feature casting for manufacture observation is disclosed herein. According to an aspect, a method includes applying a molding material to a feature of a circuit to substantially cover the feature with the molding material. The method also includes curing the molding material. Further, the method includes separating the molding material from the feature to reveal a cast of the feature of the circuit.

公开(公告)号：US20180220527A1

公开(公告)日：2018-08-02

申请号：US15940314

申请日：2018-03-29

申请人： DELL PRODUCTS, LP

发明人： Stuart Allen Berke ,  Sandor Farkas ,  Bhyrav M. Mutnury

IPC分类号： H05K1/02 ,  H05K3/42 ,  H05K1/09

CPC分类号： H05K1/0251 ,  H05K1/09 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10T29/49004

摘要： A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.