公开(公告)号：US20120030519A1

公开(公告)日：2012-02-02

申请号：US12847687

申请日：2010-07-30

申请人： Nicholas Wilt ,  Scott Gray

发明人： Nicholas Wilt ,  Scott Gray

IPC分类号： G06F11/30 ,  G06F9/40

CPC分类号： G06F11/1645 ,  G06F11/1637

摘要： A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

摘要翻译： 提供了一种自检网络，包括被配置为执行演奏功能的第一命令处理器和被配置为执行与第一命令处理器耦合的演奏功能的第二命令处理器。 自检网络还包括被配置为执行耦合到第一命令处理器的监视功能的第一监视器处理器和被配置为执行耦合到第二命令处理器的监视功能的第二监视器处理器。 第一和第二命令处理器比较输出，第一和第二监视器处理器比较输出，并且第一监视器处理器确定第一命令处理器的输出是否超过第一选择的限制。

公开(公告)号：US20110214043A1

公开(公告)日：2011-09-01

申请号：US12713712

申请日：2010-02-26

申请人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

发明人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

IPC分类号： G06F11/07

CPC分类号： G06F11/1645 ,  G06F11/1625 ,  H04L1/244

摘要： Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

摘要翻译： 提供了用于验证跨多轨数据总线传输的信号的完整性的方法和装置。 该方法和装置提供由第一处理器和第二处理器独立地处理信号，第一和第二处理器并联连接，从而产生第一处理信号和第二处理信号。 每个经处理的信号被分成第一组分序列和第二组分序列，第一组分序列不同于第二组分序列。 然后确定第一组分序列不相同，并且第二组分序列不相同。 如果第一分量序列中的任一个不相同，或者如果第二分量序列中的任一个不相同，则通过总线的第一或第二轨道向接收设备发送错误信号。

公开(公告)号：US08316192B2

公开(公告)日：2012-11-20

申请号：US12575709

申请日：2009-10-08

申请人： Scott Gray ,  Nicholas Wilt

发明人： Scott Gray ,  Nicholas Wilt

IPC分类号： G06F12/00

CPC分类号： G11C8/16 ,  G06F13/1684

摘要： Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

摘要翻译： 提供了改进多端口存储器的系统和方法。 在一个实施例中，处理系统包括：至少一个处理核心; 外围总线 以及用于存储数字数据的存储器，所述存储器被分成存储器段的第一和第二分区。 存储器包括耦合到外围总线的第一端口，仅提供对第一分区的读访问和写访问，其中第一分区存储与耦合到外围总线的一个或多个外围组件相关联的外围数据; 耦合到所述至少一个处理器的第二端口，其提供仅对所述第二分区的只读访问，其中所述第二分区存储用于所述至少一个处理核心的可执行代码; 以及耦合到所述至少一个处理器的第三端口，其提供对所述整个第一分区和所述第二分区的读访问和写访问。

公开(公告)号：US08499193B2

公开(公告)日：2013-07-30

申请号：US12847687

申请日：2010-07-30

申请人： Nicholas Wilt ,  Scott Gray

发明人： Nicholas Wilt ,  Scott Gray

IPC分类号： G06F11/00

CPC分类号： G06F11/1645 ,  G06F11/1637

摘要： A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

摘要翻译： 提供了一种自检网络，包括被配置为执行演奏功能的第一命令处理器和被配置为执行与第一命令处理器耦合的演奏功能的第二命令处理器。 自检网络还包括被配置为执行耦合到第一命令处理器的监视功能的第一监视器处理器和被配置为执行耦合到第二命令处理器的监视功能的第二监视器处理器。 第一和第二命令处理器比较输出，第一和第二监视器处理器比较输出，并且第一监视器处理器确定第一命令处理器的输出是否超过第一选择的限制。

公开(公告)号：US20110087847A1

公开(公告)日：2011-04-14

申请号：US12575709

申请日：2009-10-08

申请人： Scott Gray ,  Nicholas Wilt

发明人： Scott Gray ,  Nicholas Wilt

IPC分类号： G06F12/10

CPC分类号： G11C8/16 ,  G06F13/1684

摘要： Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

摘要翻译： 提供了改进多端口存储器的系统和方法。 在一个实施例中，处理系统包括：至少一个处理核心; 外围总线 以及用于存储数字数据的存储器，所述存储器被分成存储器段的第一和第二分区。 存储器包括耦合到外围总线的第一端口，仅提供对第一分区的读访问和写访问，其中第一分区存储与耦合到外围总线的一个或多个外围组件相关联的外围数据; 耦合到所述至少一个处理器的第二端口，其提供仅对所述第二分区的只读访问，其中所述第二分区存储用于所述至少一个处理核心的可执行代码; 以及耦合到所述至少一个处理器的第三端口，其提供对所述整个第一分区和所述第二分区的读访问和写访问。

公开(公告)号：US20060136359A1

公开(公告)日：2006-06-22

申请号：US11019691

申请日：2004-12-21

申请人： Nicholas Wilt ,  Steven Thompson ,  Scott Gray

发明人： Nicholas Wilt ,  Steven Thompson ,  Scott Gray

IPC分类号： G06F17/30

CPC分类号： G05B23/0208 ,  G01N2035/00881 ,  G01N2203/0055 ,  G01N2203/021 ,  G01N2203/0244 ,  G01N2203/0658

摘要： A method for initializing a chain of non-initialized data collectors is disclosed. The chain of non-initialized data collectors are coupled to a controller. In a first step communication between the controller and each data collector in the chain of non-initialized collectors is disabled, except for an active non-initialized data collector, The active non-initialized collector is coupled to the controller and any remaining non-initialized data collectors. Next, the active non-initialized data collector is initialized by assigning an identification number to the active non-initialized data collectors. The active non-initialized collector becomes an initialized data collector. Then, communication is restored between the initialized data collector and a next active non-initialized data collector in the chain of non-initialized data collectors. The method repeats until all non-initialized data collectors are initialized.

公开(公告)号：US08365024B2

公开(公告)日：2013-01-29

申请号：US12713712

申请日：2010-02-26

申请人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

发明人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

IPC分类号： G01R31/28 ,  G06F7/02 ,  H03M13/00

CPC分类号： G06F11/1645 ,  G06F11/1625 ,  H04L1/244

摘要： Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

摘要翻译： 提供了用于验证跨多轨数据总线传输的信号的完整性的方法和装置。 该方法和装置提供由第一处理器和第二处理器独立地处理信号，第一和第二处理器并联连接，从而产生第一处理信号和第二处理信号。 每个经处理的信号被分成第一组分序列和第二组分序列，第一组分序列不同于第二组分序列。 然后确定第一组分序列不相同，并且第二组分序列不相同。 如果第一分量序列中的任一个不相同，或者如果第二分量序列中的任一个不相同，则通过总线的第一或第二轨道向接收设备发送错误信号。

公开(公告)号：US20130191584A1

公开(公告)日：2013-07-25

申请号：US13355721

申请日：2012-01-23

申请人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

发明人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

IPC分类号： G06F12/02

CPC分类号： G06F11/1645 ,  G06F11/1679 ,  G06F15/167

摘要： Systems integrated into a single electronic chip are provided for. The systems include a primary shared bus, a secondary shared bus and an embedded dynamic random access memory (eDRAM) including a first port and a second port. The systems also include a primary processor in operable communication with the eDRAM via the first port; and a secondary processor in operable communication with the eDRAM via the secondary bus and the second port, wherein the primary and secondary processors are operating in synchronization.

摘要翻译： 提供集成到单个电子芯片中的系统。 该系统包括主共享总线，辅助共享总线和包括第一端口和第二端口的嵌入式动态随机存取存储器（eDRAM）。 所述系统还包括通过第一端口与eDRAM可操作地通信的主处理器; 以及经由次级总线和第二端口与eDRAM可操作地通信的辅助处理器，其中主处理器和次处理器同步操作。

公开(公告)号：US08423717B2

公开(公告)日：2013-04-16

申请号：US12629325

申请日：2009-12-02

申请人： Scott Gray ,  Nicholas Wilt

发明人： Scott Gray ,  Nicholas Wilt

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F9/468 ,  G06F12/0842

摘要： A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.

摘要翻译： 多核处理器芯片包括具有多个端口和多个地址空间和多个处理器核心的至少一个共享高速缓存。 每个处理器核心耦合到所述多个端口中的一个，使得每个处理器核能够与所述多个处理器核心中的另一个同时存取所述至少一个共享高速缓存。 每个处理器核心被分配为唯一应用程序或唯一应用程序任务之一，并且多核处理器可操作以执行分区操作系统，其在每个唯一应用程序和每个唯一应用程序任务上进行时间上和空间上的隔离，使得多个处理器 核心不试图与多个处理器核心中的另一个同时写入至少一个共享高速缓存的同一地址空间。

公开(公告)号：US20110131377A1

公开(公告)日：2011-06-02

申请号：US12629325

申请日：2009-12-02

申请人： Scott Gray ,  Nicholas Wilt

发明人： Scott Gray ,  Nicholas Wilt

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/084 ,  G06F9/468 ,  G06F12/0842

摘要： A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.

摘要翻译： 多核处理器芯片包括具有多个端口和多个地址空间和多个处理器核心的至少一个共享高速缓存。 每个处理器核心耦合到所述多个端口中的一个，使得每个处理器核能够与所述多个处理器核心中的另一个同时存取所述至少一个共享高速缓存。 每个处理器核心被分配为唯一应用程序或唯一应用程序任务之一，并且多核处理器可操作以执行分区操作系统，其在每个唯一应用程序和每个唯一应用程序任务上进行时间上和空间上的隔离，使得多个处理器 核心不试图与多个处理器核心中的另一个同时写入至少一个共享高速缓存的同一地址空间。