-
公开(公告)号：US20110061030A1
公开(公告)日：2011-03-10
申请号：US12555219
申请日：2009-09-08
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.
摘要翻译： 公开了用于验证光掩模设计的解决方案。 在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。
-
公开(公告)号：US08166423B2
公开(公告)日：2012-04-24
申请号：US12555219
申请日：2009-09-08
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.
摘要翻译： 公开了用于验证光掩模设计的解决方案。 在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。
-
公开(公告)号：US20080141211A1
公开(公告)日：2008-06-12
申请号：US11609033
申请日：2006-12-11
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.
摘要翻译： 提供了一种用于执行光学邻近校正（“OPC”）验证的方法，其中使用与光掩模的形状，使用光掩模获得的空间图像或光致抗蚀剂图像相关联的数据来识别光掩模的特征 使用光掩模在可光成像层中获得。 识别光掩模，空中图像或光致抗蚀剂图像的多个区域，其包含所识别的关注特征，其中多个识别区域占据占据特征的光掩模的总面积的面积实质上更小的面积。 然后执行限于多个所识别的区域的增强的OPC验证，以识别光掩模，空中图像或光致抗蚀剂图像中的至少一个的问题。
-
公开(公告)号：US07562337B2
公开(公告)日：2009-07-14
申请号：US11609033
申请日：2006-12-11
CPC分类号： G03F1/36
摘要： A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.
摘要翻译： 提供了一种用于执行光学邻近校正（“OPC”）验证的方法，其中使用与光掩模的形状，使用光掩模获得的空间图像或光致抗蚀剂图像相关联的数据来识别光掩模的特征 使用光掩模在可光成像层中获得。 识别光掩模，空中图像或光致抗蚀剂图像的多个区域，其包含所识别的关注特征，其中多个识别区域占据占据特征的光掩模的总面积的面积实质上更小的面积。 然后执行限于多个所识别的区域的增强的OPC验证，以识别光掩模，空中图像或光致抗蚀剂图像中的至少一个的问题。
-
公开(公告)号：US20090037867A1
公开(公告)日：2009-02-05
申请号：US11833465
申请日：2007-08-03
申请人： Gregory J. Dick
发明人： Gregory J. Dick
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing and forming a mask used for projecting an image of an integrated circuit design. After providing a mask element corresponding to a portion of a design of an integrated circuit layout, the method includes correcting the mask element using OPC techniques, and fracturing the OPC-corrected mask element into a plurality of polygonal segments. The method then includes identifying along an edge of the mask element a polygon edge having a thickness less than that which can be normally reproduced by a mask writer, and modifying configuration of the identified mask element segment to add or subtract length to an end of the polygon to create a corrected mask element having increased resolution by the mask writer. The method then includes using an electron beam or other mask writer to form a mask having the mask element with modified configuration.
摘要翻译： 一种设计和形成用于投影集成电路设计图像的掩模的方法。 在提供与集成电路布局的设计的一部分相对应的掩模元件之后，该方法包括使用OPC技术校正掩模元件，并将OPC校正的掩模元件压裂成多个多边形段。 该方法然后包括沿着掩模元件的边缘识别具有小于可由掩模写入器正常再现的厚度的多边形边缘，以及修改所识别的掩模元素段的配置以将长度加或减 多边形以通过掩模写入器创建具有增加的分辨率的校正的蒙版元素。 该方法然后包括使用电子束或其它掩模写入器来形成具有修改结构的掩模元件的掩模。
-
公开(公告)号：US5309354A
公开(公告)日：1994-05-03
申请号：US784834
申请日：1991-10-30
申请人： Gregory J. Dick
发明人： Gregory J. Dick
IPC分类号： H01L21/027 , H01J37/302 , G06F15/46
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J37/3026 , H01J2237/31761 , H01J2237/31769
摘要： A more efficient method of macro placement and graying for electron beam (e-beam) lithography. The e-beam field is divided into smaller subfields. Repetitious shapes or collections of shapes which are repetitious are represented by macros. Some shapes span or are intersected by subfield boundaries. After the shapes are converted to fill rectangles and the fill rectangles are proximity corrected, the macro containing the proximity corrected fill rectangles is grayed and placed without being unnested. First, the Macro Organization Step, the macro's fill rectangles are sorted. Tall-narrow macros are sorted top to bottom then left to right, short-wide macros are sorted left to right then top to bottom. After the sort, chains of rectangles are created and a shadow is generated for the macro and for each chain. Next, the Macro Placement and Graying Step, a determination is made of whether and where macro graying will be required. The macro shadow is transformed into subfield coordinates and a determination is made of whether the transformed shadow intersects with (spans) a subfield boundary. If the macro's shadow touches more than one subfield (spans a subfield boundary), then the macro's chain shadows are examined to determine if any chain spans the boundary. Graying is done on any spanning chain. Gray-spliced rectangles and single rectangles are placed in the pattern buffer. Partial macro read commands are placed in the pattern buffer for chains or partial chains resulting from gray-splicing.
摘要翻译： 用于电子束（e-beam）光刻的更有效的宏放置和灰化方法。 电子束场被分成较小的子场。 重复的形状或重复的形状的集合由宏表示。 一些形状跨越或与子场边界相交。 在将形状转换为填充矩形并且填充矩形被近似校正之后，包含接近校正的填充矩形的宏被灰化并放置而不被不必要地排列。 首先，宏组织步骤，宏的填充矩形被排序。 高大的宏从上到下排列，从左到右排列，短宽宏从左到右排列，从上到下排列。 排序后，将创建矩形链，并为宏和每个链生成阴影。 接下来，宏放置和灰化步骤，确定是否和何处需要宏灰色。 宏影子被转换成子场坐标，并且确定变换的阴影是否与子场边界相交（跨度）。 如果宏的阴影触及不止一个子域（跨越子域边界），则检查宏的链影，以确定是否有任何链跨越边界。 灰色在任何跨越链上完成。 灰色拼接矩形和单个矩形放置在图案缓冲区中。 部分宏读取命令放置在由灰色拼接产生的链或部分链的模式缓冲区中。
-
公开(公告)号：US07694268B2
公开(公告)日：2010-04-06
申请号：US11833465
申请日：2007-08-03
申请人： Gregory J. Dick
发明人： Gregory J. Dick
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing and forming a mask used for projecting an image of an integrated circuit design. After providing a mask element corresponding to a portion of a design of an integrated circuit layout, the method includes correcting the mask element using OPC techniques, and fracturing the OPC-corrected mask element into a plurality of polygonal segments. The method then includes identifying along an edge of the mask element a polygon edge having a thickness less than that which can be normally reproduced by a mask writer, and modifying configuration of the identified mask element segment to add or subtract length to an end of the polygon to create a corrected mask element having increased resolution by the mask writer. The method then includes using an electron beam or other mask writer to form a mask having the mask element with modified configuration.
摘要翻译： 一种设计和形成用于投影集成电路设计图像的掩模的方法。 在提供与集成电路布局的设计的一部分相对应的掩模元件之后，该方法包括使用OPC技术校正掩模元件，并将OPC校正的掩模元件压裂成多个多边形段。 该方法然后包括沿着掩模元件的边缘识别具有小于可由掩模写入器正常再现的厚度的多边形边缘，以及修改所识别的掩模元素段的配置以将长度加或减 多边形以通过掩模写入器创建具有增加的分辨率的校正的蒙版元素。 该方法然后包括使用电子束或其它掩模写入器来形成具有修改结构的掩模元件的掩模。
-
公开(公告)号：US5526279A
公开(公告)日：1996-06-11
申请号：US310463
申请日：1994-09-22
申请人： Gregory J. Dick
发明人： Gregory J. Dick
IPC分类号： G06F17/50 , H01L23/528
CPC分类号： G06F17/5081
摘要： A technique allows for processing all the original cells of an integrated circuit design without any partial unnesting. In the first step, each nested cell is framed by a bounding box or polygon which contains all the shapes in the cell. In the second step, an overlap removal is performed on the frames. In the third step, for each cell, the shapes within the original frame and any other shapes intruding on the overlap removed frame are retrieved. In the fourth step, overlap removal (or union) is performed on the shapes retrieved in the third step. The overlap removed frame will clip off any pieces outside. Union will integrate any non-original shapes into the cell. After the third and fourth steps have been performed for all cells, the modified cells will contain all the original shape information and are independent.
摘要翻译： 一种技术允许对集成电路设计的所有原始单元进行处理，而不会发生任何部分不了解。 在第一步中，每个嵌套单元格由包含单元格中所有形状的边界框或多边形构成。 在第二步中，对帧执行重叠移除。 在第三步中，对于每个单元，检索原始框架内的形状和侵入重叠移除框架中的任何其他形状。 在第四步骤中，对在第三步骤检索的形状执行重叠移除（或联合）。 重叠移除的框架将剪除外部的任何部分。 联盟将任何非原始形状整合到单元格中。 在对所有单元执行第三和第四步骤之后，修改的单元格将包含所有原始形状信息并且是独立的。
-
9.发明授权公开(公告)号：US06177680B1
公开(公告)日：2001-01-23
申请号：US09197167
申请日：1998-11-20
IPC分类号： H01J37302
CPC分类号： H01J37/304 , G05B2219/37097 , G05B2219/37129 , G05B2219/37576 , G05B2219/45027 , H01J2237/30444 , H01J2237/3175
摘要： An e-beam system for making masks corrects the beam for pattern-dependent errors by executing the bulk of the post-processing program only once, with two sets of output data being generated by the encode routine. A first output file of the encode routine generates the beam control data without pattern-dependent corrections. A second output file merges the beam control data with the data for metrology marks. A test wafer is patterned using the second output file and measured to generate a set of pattern correction data. Production wafers are written using the beam control data corrected on the fly by the pattern correction data.
摘要翻译： 用于制造掩模的电子束系统通过仅执行一次后处理程序的大部分，由编码例程生成两组输出数据来校正波束的图形相关错误。 编码例程的第一输出文件产生不具有模式相关校正的波束控制数据。 第二个输出文件将光束控制数据与计量标记的数据进行合并。 使用第二输出文件对测试晶片进行图案化并被测量以产生一组图案校正数据。 使用通过模式校正数据在飞行中校正的波束控制数据来写入生产晶片。
-
公开(公告)号：US6091072A
公开(公告)日：2000-07-18
申请号：US956825
申请日：1997-10-23
IPC分类号： H01J37/302
CPC分类号： H01J37/3026 , H01J2237/31764
摘要： A system and method of converting large Integrated Circuit (IC) designs into patterns. First, based on shape density, the design is fragmented into pieces, each piece including roughly the same number of shapes. Next, a band of shapes, all within the proximity correction area for each piece, are identified. Each piece, including its identified band, is processed individually to convert data within the piece and within the proximity correction band to Numerical Control (NC) data. The NC data for the proximity correction band is discarded. The piece's NC data is stored as an NC data file for the piece. This is repeated until all of the pieces are converted to NC data. Finally, the pattern is written, one piece at a time.
摘要翻译： 将大型集成电路（IC）设计转换为模式的系统和方法。 首先，基于形状密度，设计被分割成片，每片包括大致相同数量的形状。 接下来，识别出每个片段的接近校正区域内的形状带。 每个片段，包括其标识的频带，被单独处理，以将该片段内的数据和接近校正频带内的数据转换为数字控制（NC）数据。 用于接近校正频带的NC数据被丢弃。 该片的NC数据存储为该片的NC数据文件。 重复此操作，直到所有片段都转换为NC数据。 最后，模式是一次写成的。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.023 秒)
