公开(公告)号：US20190212387A1

公开(公告)日：2019-07-11

申请号：US15864584

申请日：2018-01-08

Applicant: Seagate Technology LLC

Inventor： Paras Gangwal ,  Komal Shah ,  Surbhi Bansal ,  Sachin Bastimane

IPC: G01R31/317 ,  G01R31/3177

Abstract: An on-chip clock (OCC) circuit of an integrated circuit includes a clock generator, an OCC controller, and an OCC observation circuit. The clock generator is configured to generate a plurality of clock signals. The OCC controller is configured to receive the clock signals and generate an OCC output for use by the scan chains of logic blocks. The OCC observation circuit is configured to generate a status output on a status output port based on the OCC output during an at-speed capture phase and a scan enable signal. Patterns of the status output with respect to the scan enable signal include a valid pattern indicating that the OCC output includes a valid number of at-speed capture pulses, a first invalid pattern indicating a first error in the OCC output, and a second invalid pattern indicating a second error in the OCC output that is different from the first error.

公开(公告)号：US10459029B2

公开(公告)日：2019-10-29

申请号：US15864584

申请日：2018-01-08

Applicant: Seagate Technology LLC

Inventor： Paras Gangwal ,  Komal Shah ,  Surbhi Bansal ,  Sachin Bastimane

IPC: G01R31/317 ,  G01R31/3177

Abstract: An on-chip clock (OCC) circuit of an integrated circuit includes a clock generator, an OCC controller, and an OCC observation circuit. The clock generator is configured to generate a plurality of clock signals. The OCC controller is configured to receive the clock signals and generate an OCC output for use by the scan chains of logic blocks. The OCC observation circuit is configured to generate a status output on a status output port based on the OCC output during an at-speed capture phase and a scan enable signal. Patterns of the status output with respect to the scan enable signal include a valid pattern indicating that the OCC output includes a valid number of at-speed capture pulses, a first invalid pattern indicating a first error in the OCC output, and a second invalid pattern indicating a second error in the OCC output that is different from the first error.

公开(公告)号：US11754624B1

公开(公告)日：2023-09-12

申请号：US17679686

申请日：2022-02-24

Applicant: Seagate Technology LLC

Inventor： Bharat Londhe ,  Deep Neema ,  Komal Shah

IPC: G01R31/3177 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/319

CPC classification number: G01R31/3177 ,  G01R31/3181 ,  G01R31/31921 ,  G01R31/318307 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318547

Abstract: A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

公开(公告)号：US20230266388A1

公开(公告)日：2023-08-24

申请号：US17679686

申请日：2022-02-24

Applicant: Seagate Technology LLC.

Inventor： Bharat Londhe ,  Deep Neema ,  Komal Shah

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

公开(公告)号：US10685730B1

公开(公告)日：2020-06-16

申请号：US15926414

申请日：2018-03-20

Applicant: Seagate Technology LLC

Inventor： Komal Shah ,  Jay Shah ,  Sachin Bastimane

IPC: G11C29/38 ,  G11C29/12 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/04

Abstract: In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.