公开(公告)号：US09385089B2

公开(公告)日：2016-07-05

申请号：US13753792

申请日：2013-01-30

Applicant: Seagate Technology LLC

Inventor： Dongsung Hong ,  Lijuan Zou ,  Daniel Sullivan ,  Lily Horng Youtt

IPC: H01L21/76 ,  H01L21/46 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer.

Abstract translation: 当不透明膜沉积在半导体晶片上时，潜在的对准标记可能被隐藏。 这种对准标记的再曝光是所得表面形貌的一个来源。 根据一个实施方案，嵌入在晶片中的对准标记可以通过从一个或多个层去除材料并且用透明材料代替这样的材料来暴露。 根据另一实施方式，可以通过选择性地在停止层上方进行灰化或蚀刻来减轻在对准标记恢复过程中去除的材料的量。

公开(公告)号：US20140209368A1

公开(公告)日：2014-07-31

申请号：US13753730

申请日：2013-01-30

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Carolyn Pitcher Van Dorn ,  Lily Horng Youtt ,  Daniel Boyd Sullivan

IPC: G11B5/127 ,  H05K13/00 ,  H05K1/11

CPC classification number: H05K1/115 ,  G11B5/102 ,  G11B5/3173 ,  G11B5/6094 ,  H05K1/0219 ,  H05K1/0259 ,  H05K1/053 ,  Y10T29/49124

Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.

Abstract translation: 在薄膜头上形成衬底电连接是所得表面形貌的一个来源。 根据一个实施方案，可以通过包括沉积第一层底漆的方法，在一个或多个电镀工艺中产生电凹槽，以及在电气通孔顶部和顶部沉积第二层底漆的方法来减少这种形貌 的第一层底漆。 在一个实施方式中，第一和第二底色层的组合高度基本上等于电气凹槽的高度。 在一个实施方案中，所得到的形貌特征足够小，使得它们可以被平坦化，而不会造成跨越晶片的总底涂层厚度的不均匀性。

公开(公告)号：US09426886B2

公开(公告)日：2016-08-23

申请号：US13753730

申请日：2013-01-30

Applicant: Seagate Technology LLC

Inventor： Carolyn Pitcher Van Dorn ,  Lily Horng Youtt ,  Daniel Boyd Sullivan

IPC: G11B5/127 ,  H05K1/11 ,  G11B5/10 ,  G11B5/31 ,  G11B5/60 ,  H05K1/02 ,  H05K1/05

CPC classification number: H05K1/115 ,  G11B5/102 ,  G11B5/3173 ,  G11B5/6094 ,  H05K1/0219 ,  H05K1/0259 ,  H05K1/053 ,  Y10T29/49124

Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.

Abstract translation: 在薄膜头上形成衬底电连接是所得表面形貌的一个来源。 根据一个实施方案，可以通过包括沉积第一层底漆的方法，在一个或多个电镀工艺中产生电凹槽，以及在电气通孔顶部和顶部沉积第二层底漆的方法来减少这种形貌 的第一层底漆。 在一个实施方式中，第一和第二底色层的组合高度基本上等于电气凹槽的高度。 在一个实施方案中，所得到的形貌特征足够小，使得它们可以被平坦化，而不会造成跨越晶片的总底涂层厚度的不均匀性。

公开(公告)号：US20140210113A1

公开(公告)日：2014-07-31

申请号：US13753792

申请日：2013-01-30

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Dongsung Hong ,  Lijuan Zou ,  Daniel Sullivan ,  Lily Horng Youtt

IPC: H01L23/544 ,  H01L21/308

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer.

Abstract translation: 当不透明膜沉积在半导体晶片上时，潜在的对准标记可能被隐藏。 这种对准标记的再曝光是所得表面形貌的一个来源。 根据一个实施方案，嵌入在晶片中的对准标记可以通过从一个或多个层去除材料并且用透明材料代替这样的材料来暴露。 根据另一实施方式，可以通过在停止层上方选择性灰化或蚀刻来减轻在对准标记恢复过程中去除的材料的量。