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公开(公告)号：US20140254338A1
公开(公告)日：2014-09-11
申请号：US13791130
申请日：2013-03-08
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Andrew David Habermas , Dongsung Hong , Daniel Boyd Sullivan
CPC classification number: G11B5/3163 , B82Y10/00 , G11B5/3116 , G11B5/314 , Y10S977/887
Abstract: Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.
Abstract translation: 纳米压印光刻可以以各种方式用于提高薄膜头制造的微电子结构的分辨率，图案保真度和对称性。 例如，写极点，读取器和近场换能器可以用更严格的公差制造，从而改善微电子结构的性能。 此外，可以使用纳米压印光刻法同时制造薄膜头的整个条，这减少或消除了薄膜头中的相邻薄膜头之间的对准误差。
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公开(公告)号：US20140209368A1
公开(公告)日：2014-07-31
申请号：US13753730
申请日：2013-01-30
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Carolyn Pitcher Van Dorn , Lily Horng Youtt , Daniel Boyd Sullivan
CPC classification number: H05K1/115 , G11B5/102 , G11B5/3173 , G11B5/6094 , H05K1/0219 , H05K1/0259 , H05K1/053 , Y10T29/49124
Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.
Abstract translation: 在薄膜头上形成衬底电连接是所得表面形貌的一个来源。 根据一个实施方案，可以通过包括沉积第一层底漆的方法，在一个或多个电镀工艺中产生电凹槽，以及在电气通孔顶部和顶部沉积第二层底漆的方法来减少这种形貌 的第一层底漆。 在一个实施方式中，第一和第二底色层的组合高度基本上等于电气凹槽的高度。 在一个实施方案中，所得到的形貌特征足够小，使得它们可以被平坦化，而不会造成跨越晶片的总底涂层厚度的不均匀性。
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公开(公告)号：US09426886B2
公开(公告)日：2016-08-23
申请号：US13753730
申请日：2013-01-30
Applicant: Seagate Technology LLC
Inventor： Carolyn Pitcher Van Dorn , Lily Horng Youtt , Daniel Boyd Sullivan
CPC classification number: H05K1/115 , G11B5/102 , G11B5/3173 , G11B5/6094 , H05K1/0219 , H05K1/0259 , H05K1/053 , Y10T29/49124
Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.
Abstract translation: 在薄膜头上形成衬底电连接是所得表面形貌的一个来源。 根据一个实施方案，可以通过包括沉积第一层底漆的方法，在一个或多个电镀工艺中产生电凹槽，以及在电气通孔顶部和顶部沉积第二层底漆的方法来减少这种形貌 的第一层底漆。 在一个实施方式中，第一和第二底色层的组合高度基本上等于电气凹槽的高度。 在一个实施方案中，所得到的形貌特征足够小，使得它们可以被平坦化，而不会造成跨越晶片的总底涂层厚度的不均匀性。
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公开(公告)号：US09343089B2
公开(公告)日：2016-05-17
申请号：US13791130
申请日：2013-03-08
Applicant: Seagate Technology LLC
Inventor： Andrew David Habermas , Dongsung Hong , Daniel Boyd Sullivan
CPC classification number: G11B5/3163 , B82Y10/00 , G11B5/3116 , G11B5/314 , Y10S977/887
Abstract: Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.
Abstract translation: 纳米压印光刻可以以各种方式用于提高薄膜头制造的微电子结构的分辨率，图案保真度和对称性。 例如，写极点，读取器和近场换能器可以用更严格的公差制造，从而改善微电子结构的性能。 此外，可以使用纳米压印光刻法同时制造薄膜头的整个条，这减少或消除了薄膜头中的相邻薄膜头之间的对准误差。
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