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公开(公告)号：US20250029646A1
公开(公告)日：2025-01-23
申请号：US18907237
申请日：2024-10-04
Applicant: Seagate Technology LLC
Inventor： Jon D. TRANTHAM , Praveeen VIRARAGHAVAN , John W. DYKES , Ian J. GILBERT , Sangita Shreedharan KALARICKAL , Matthew J. TOTIN , Mohamad EL-BATAL , Darshana H. MEHTA
Abstract: A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation.
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公开(公告)号：US20250104793A1
公开(公告)日：2025-03-27
申请号：US18907337
申请日：2024-10-04
Applicant: Seagate Technology LLC
Inventor： Jon D. TRANTHAM , Praveeen VIRARAGHAVAN , John W. DYKES , Ian J. GILBERT , Sangita Shreedharan KALARICKAL , Matthew J. TOTIN , Mohamad EL-BATAL , Darshana H. MEHTA
Abstract: A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.
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公开(公告)号：US20240070070A1
公开(公告)日：2024-02-29
申请号：US18503118
申请日：2023-11-06
Applicant: Seagate Technology LLC
Inventor： Jon D. TRANTHAM , Praveen VIRARAGHAVAN , John W. DYKES , Ian J. GILBERT , Sangita Shreedharan KALARICKAL , Matthew J. TOTIN , Mohamad EL-BATAL , Darshana H. MEHTA
IPC: G06F12/0802 , G06F3/06
CPC classification number: G06F12/0802 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F2212/60
Abstract: Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.
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