公开(公告)号：US20180335961A1

公开(公告)日：2018-11-22

申请号：US15597881

申请日：2017-05-17

Applicant: Seagate Technology LLC

Inventor： Phillip R. Colline ,  Michael Barrell

IPC: G06F3/06 ,  G06F13/42

Abstract: A data storage network may have multiple data storage devices that each consist of a device buffer. A network buffer and buffer circuit can be found in a network controller with the buffer circuit arranged to divide and store data associated with a data access request in the network buffer and the device buffer of the first data storage device.

公开(公告)号：US20200089609A1

公开(公告)日：2020-03-19

申请号：US16135576

申请日：2018-09-19

Applicant: Seagate Technology LLC

Inventor： Phillip R. Colline ,  Michael Barrell ,  Richard O. Weiss ,  Mohamad H. El-Batal

IPC: G06F12/0804 ,  G06F13/16 ,  G06F13/42

Abstract: A data storage system can have one or more hosts connected to a data storage subsystem with the host having a host processor and the data storage subsystem having a controller. Write back data generated at the host triggers the host processor to allocate a cache location in the data storage subsystem where the generated data is subsequently stored. The generated write back data is written in a non-volatile destination address as directed by the controller prior to waiting for a secondary event with the generated data stored in both the cache location and the non-volatile destination address. Detection of the secondary event prompts the controller to signal the host processor that the cache location is free for new data.

公开(公告)号：US20240020050A1

公开(公告)日：2024-01-18

申请号：US17864900

申请日：2022-07-14

Applicant: Seagate Technology, LLC

Inventor： Phillip R. Colline ,  Timothy Ted Walker ,  Steven Williams ,  Hemant Vitthalrao Mane ,  Jason Matthew Feist

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

Abstract: Apparatus and method for executing controller memory buffer (CMB) based data transfer commands in a distributed data processing environment. In some embodiments, a storage device having a device controller and a main non-volatile memory (NVM) is coupled to a client device via an interface. The client device respectively issues normal data transfer commands and bypass data transfer commands to the storage device. The normal data transfer commands include read and write commands that result in transfer of data between the NVM and the client device using a normal data path through the storage device. The bypass data transfer commands involve an allocated CMB of the storage device directly controlled and accessed by the client device. In this way, write data are directly placed into the CMB for writing to the NVM, and readback data from the NVM are directly recovered from the CMB by the client device.

公开(公告)号：US20190065488A1

公开(公告)日：2019-02-28

申请号：US15689395

申请日：2017-08-29

Applicant: Seagate Technology LLC

Inventor： Phillip R. Colline

IPC: G06F17/30 ,  G06F11/07

Abstract: A write command includes data targeted to a data sector of a non-volatile memory. The data is committed to be stored in the data sector. Protection information bytes of the data are stored together with the data in the data sector, and the protection information bytes are copied to a distilled protection sector. A read request is received for the data and in response, the protection information in the data sector is validated against the copy of the protection information in the distilled protection sector.

公开(公告)号：US12260117B2

公开(公告)日：2025-03-25

申请号：US17864900

申请日：2022-07-14

Applicant: Seagate Technology, LLC

Inventor： Phillip R. Colline ,  Timothy Ted Walker ,  Steven Williams ,  Hemant Vitthalrao Mane ,  Jason Matthew Feist

IPC: G06F3/00 ,  G06F3/06

Abstract: Apparatus and method for executing controller memory buffer (CMB) based data transfer commands in a distributed data processing environment. In some embodiments, a storage device having a device controller and a main non-volatile memory (NVM) is coupled to a client device via an interface. The client device respectively issues normal data transfer commands and bypass data transfer commands to the storage device. The normal data transfer commands include read and write commands that result in transfer of data between the NVM and the client device using a normal data path through the storage device. The bypass data transfer commands involve an allocated CMB of the storage device directly controlled and accessed by the client device. In this way, write data are directly placed into the CMB for writing to the NVM, and readback data from the NVM are directly recovered from the CMB by the client device.

公开(公告)号：US11803468B2

公开(公告)日：2023-10-31

申请号：US16135576

申请日：2018-09-19

Applicant: Seagate Technology LLC

Inventor： Phillip R. Colline ,  Michael Barrell ,  Richard O. Weiss ,  Mohamad H. El-Batal

IPC: G06F12/00 ,  G06F12/0804 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/0804 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2212/1032 ,  G06F2213/0026

Abstract: A data storage system can have one or more hosts connected to a data storage subsystem with the host having a host processor and the data storage subsystem having a controller. Write back data generated at the host triggers the host processor to allocate a cache location in the data storage subsystem where the generated data is subsequently stored. The generated write back data is written in a non-volatile destination address as directed by the controller prior to waiting for a secondary event with the generated data stored in both the cache location and the non-volatile destination address. Detection of the secondary event prompts the controller to signal the host processor that the cache location is free for new data.

公开(公告)号：US11287985B2

公开(公告)日：2022-03-29

申请号：US15597881

申请日：2017-05-17

Applicant: Seagate Technology LLC

Inventor： Phillip R. Colline ,  Michael Barrell

IPC: G06F3/06 ,  G06F13/42

Abstract: A data storage network may have multiple data storage devices that each consist of a device buffer. A network buffer and buffer circuit can be found in a network controller with the buffer circuit arranged to divide and store data associated with a data access request in the network buffer and the device buffer of the first data storage device.