公开(公告)号：US20220244851A1

公开(公告)日：2022-08-04

申请号：US17165675

申请日：2021-02-02

Applicant: Seagate Technology LLC

Inventor： Hemant MANE ,  Rajesh Maruti BHAGWAT ,  Avinash Suresh PISAL ,  Niranjan Anant POL

IPC: G06F3/06 ,  G06F13/10 ,  G06F13/42

Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

公开(公告)号：US20250028460A1

公开(公告)日：2025-01-23

申请号：US18777218

申请日：2024-07-18

Applicant: Seagate Technology LLC

Inventor： Avinash Suresh PISAL ,  Rajesh Maruti BHAGWAT

IPC: G06F3/06

Abstract: The system disclosed herein includes one or more storage drives, an FPGA based controller board, and a flash memory configured to store one or more FPGA executable binary libraries. The FPGA based controller board may include a drive logic detector configured to detect the type of the one or more of the storage drives and an FPGA executable libraries configuration module configured to select one or more of the FPGA executable binary libraries from the flash memory based on the type of the one or more of the storage drives to implement an FPGA based interface for communication between the one or more storage drives and a host.

公开(公告)号：US20230152970A1

公开(公告)日：2023-05-18

申请号：US17564052

申请日：2021-12-28

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti BHAGWAT ,  Nahoosh Hemchandra MANDLIK ,  Niranjan Anant POL ,  Hemantkumar Vitthalrao Mane

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679

Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.