ON-CHIP NVM ISP EMULATION IN FPGA

    公开(公告)号:US20220244851A1

    公开(公告)日:2022-08-04

    申请号:US17165675

    申请日:2021-02-02

    Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

    COMPUTATIONAL STORAGE DRIVE USING FPGA IMPLEMENTED INTERFACE

    公开(公告)号:US20230112448A1

    公开(公告)日:2023-04-13

    申请号:US17563999

    申请日:2021-12-28

    Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide one or more data management functionality. The CSD interfaces with a plurality of storage controllers for parallel data management functionality applied to a corresponding plurality of memory devices. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.

    ON DEMAND CONFIGURATION OF FPGA INTERFACES
    3.
    发明公开

    公开(公告)号:US20230152970A1

    公开(公告)日:2023-05-18

    申请号:US17564052

    申请日:2021-12-28

    CPC classification number: G06F3/0607 G06F3/0629 G06F3/0659 G06F3/0679

    Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.

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