摘要:
Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.
摘要:
Provided is a transformer-based oscillator which is suited to oscillate frequencies in multiple bands. An oscillator includes a transformer resonance unit and a plurality of complementary transistors. The transformer resonance unit includes a primary coil and a secondary coil corresponding to the primary coil. The plurality of complementary transistors have gates and drains between which both ends of the transformer resonance unit are respectively connected. Thus, the oscillator may operate in a differential mode or common mode according to the phase of the transformer resonance unit. Also, a complementary transistor constituting a multiband oscillation loop may be independently connected to both ends of the transformer resonance unit, and an oscillation loop of at least one band may be selected out of a multiband oscillation loop using a switch unit. Thus, the oscillator may be suited to oscillate resonance frequencies in multiple bands.
摘要:
Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.
摘要:
Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.