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    Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees
    5.
    发明申请
    Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
    用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法

    公开(公告)号：US20080143416A1

    公开(公告)日：2008-06-19

    申请号：US11610848

    申请日：2006-12-14

    申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F1/04 ,  G06F1/10

    CPC分类号： G06F1/10

    摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

    摘要翻译： 公开了一种用于提供平衡负载的时钟分配网络，结构和方法。 特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
    8.
    发明申请
    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
    集成电路供电结构

    公开(公告)号：US20090024972A1

    公开(公告)日：2009-01-22

    申请号：US12163025

    申请日：2008-06-27

    申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/206 ,  Y02D10/16 ,  Y10T307/773

    摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

    摘要翻译： 公开了对集成电路（IC）供电的设计结构，方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
    10.
    发明申请
    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
    用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构

    公开(公告)号：US20080229265A1

    公开(公告)日：2008-09-18

    申请号：US12129748

    申请日：2008-05-30

    申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G06F17/5045

    摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

    摘要翻译： 公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。 特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。