公开(公告)号：US07774573B2

公开(公告)日：2010-08-10

申请号：US10562887

申请日：2004-06-30

申请人： Sergei Sawitzki ,  Cornelis Hermanus Van Berkel

发明人： Sergei Sawitzki ,  Cornelis Hermanus Van Berkel

IPC分类号： G06F12/00

CPC分类号： G06F5/10

摘要： The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A) are provided for addressing said memory (EM) so as to operate said register memory sections as shift registers and to map shift register accesses of the at least one access port (P1 to PZ) to predetermined addresses in the global address space of the memory (EM). In this way, it is possible to combine a plurality of FIFO memories in a single addressable memory device. This implementation is favourable in view of power consumption and area. Furthermore, by introducing a buffer memory, a multi-port memory device can be replaced by a single-port memory device of the same capacity. This advanced implementation also provides a reduced cycle and access time.

摘要翻译： 本发明涉及一种包括具有至少两个可由各个地址范围AS1-ASz寻址的预定寄存器存储器区域的存储器（EM））和至少一个访问端口（P1-PZ）的存储设备，用于提供对所述存储器 ）。 此外，提供访问控制装置（A）用于寻址所述存储器（EM），以便将所述寄存器存储器部分作为移位寄存器操作，并将至少一个访问端口（P1至PZ）的移位寄存器访问映射到预定地址 存储器（EM）的全局地址空间。 以这种方式，可以在单个可寻址存储器件中组合多个FIFO存储器。 考虑到功耗和面积，这种实现是有利的。 此外，通过引入缓冲存储器，可以由相同容量的单端口存储器件替换多端口存储器件。 这种高级实现还提供了减少的周期和访问时间。

公开(公告)号：US20070205921A1

公开(公告)日：2007-09-06

申请号：US10599646

申请日：2005-04-01

申请人： Sergei Sawitzki

发明人： Sergei Sawitzki

IPC分类号： H03M7/00

CPC分类号： H03M13/4169 ,  H03M13/395 ,  H03M13/41 ,  H03M13/6561 ,  H03M13/6569

摘要： High-speed decoding with minimal footprint is achieved by parallel, separate, Viterbi decoders each processing a pair of symbols for each trellis. A two-decoder embodiment for a base band chip is utilizable for ultra wideband communication.

摘要翻译： 通过并行，独立的维特比解码器实现了具有最小占地面积的高速解码，每个解码器为每个网格处理一对符号。 用于基带芯片的双解码器实施例可用于超宽带通信。

公开(公告)号：US20060155927A1

公开(公告)日：2006-07-13

申请号：US10562887

申请日：2004-06-30

申请人： Sergei Sawitzki ,  Cornelis Van Berkel

发明人： Sergei Sawitzki ,  Cornelis Van Berkel

IPC分类号： G06F12/00

CPC分类号： G06F5/10

摘要： The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A) are provided for addressing said memory (EM) so as to operate said register memory sections as shift registers and to map shift register accesses of the at least one access port (P1 to PZ) to predetermined addresses in the global address space of the memory (EM). In this way, it is possible to combine a plurality of FIFO memories in a single addressable memory device. This implementation is favourable in view of power consumption and area. Furthermore, by introducing a buffer memory, a multi-port memory device can be replaced by a single-port memory device of the same capacity. This advanced implementation also provides a reduced cycle and access time.

摘要翻译： 本发明涉及一种存储器件，其包括具有可由各个地址范围AS 1 -ASz寻址的至少两个预定寄存器存储器部分的存储器（EM））和用于提供对所述存储器的访问的至少一个访问端口（P 1 -PZ） （EM）。 此外，提供访问控制装置（A）用于寻址所述存储器（EM），以便将所述寄存器存储器部分作为移位寄存器进行操作，并将至少一个访问端口（P 1至PZ）的移位寄存器访问映射到预定地址 在存储器（EM）的全局地址空间中。 以这种方式，可以在单个可寻址存储器件中组合多个FIFO存储器。 考虑到功耗和面积，这种实现是有利的。 此外，通过引入缓冲存储器，可以由相同容量的单端口存储器件替换多端口存储器件。 这种高级实现还提供了减少的周期和访问时间。