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公开(公告)号：US08667375B2
公开(公告)日：2014-03-04
申请号：US13367059
申请日：2012-02-06
Applicant: Sergiu Goma , Milivoje Aleksic
Inventor： Sergiu Goma , Milivoje Aleksic
IPC: H03M13/03
CPC classification number: H04L1/0057 , H03M13/19 , H03M13/27 , H04L1/0083
Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.
Abstract translation: 为了导出用于管理数据错误的汉明码，为奇偶校验位选择一组至少四个奇偶校验位位置，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。 确定每个数据位位置的综合征。 这涉及选择至少三个奇偶校验位位置的唯一子集。 唯一子集与至少一个其他唯一的至少三个奇偶校验位位置的子集共享至少一个奇偶校验位位置。 然后可以基于所确定的校正子针对每个奇偶校验位位置计算奇偶校验位值。 分组的报头可以被提供有定义分组的长度的单词和使用该单词生成的错误管理代码，从而可以检测单词中的错误并且可能被校正。
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公开(公告)号：US20130010168A1
公开(公告)日：2013-01-10
申请号：US13495518
申请日：2012-06-13
Applicant: Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
Inventor： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
CPC classification number: G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
Abstract translation: 图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合显示串行接口协议的半双工双向串行链路和符合相机的单向串行链路 串行接口协议 GMIC通过半双工双向串行链路从主机接收数据包，并处理这些数据包。 GMIC通过单向串行链路发送数据包。 来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包以启动主机存储器操作，并且可以通过双向串行链路连接到显示器，并且可以通过单向串行链路和允许主机的双向控制链路连接到摄像机 来控制显示器和相机。
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公开(公告)号：US07596743B2
公开(公告)日：2009-09-29
申请号：US11236921
申请日：2005-09-28
Applicant: Sergiu Goma , Milivoje Aleksic
Inventor： Sergiu Goma , Milivoje Aleksic
IPC: H03M13/00
CPC classification number: H04L1/0057 , H03M13/19 , H03M13/27 , H04L1/0083
Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.
Abstract translation: 为了导出用于管理数据错误的汉明码，为奇偶校验位选择一组至少四个奇偶校验位位置，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。 确定每个数据位位置的综合征。 这涉及选择至少三个奇偶校验位位置的唯一子集。 唯一子集与至少一个其他唯一的至少三个奇偶校验位位置的子集共享至少一个奇偶校验位位置。 然后可以基于所确定的校正子针对每个奇偶校验位位置计算奇偶校验位值。 分组的报头可以被提供有定义分组的长度的单词和使用该单词生成的错误管理代码，从而可以检测单词中的错误并且可能被校正。
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公开(公告)号：US20070165962A1
公开(公告)日：2007-07-19
申请号：US11332001
申请日：2006-01-13
Applicant: Maxim Smirnov , Milivoje Aleksic , Sergiu Goma
Inventor： Maxim Smirnov , Milivoje Aleksic , Sergiu Goma
IPC: G06K9/40
CPC classification number: G06K9/40 , G06T5/002 , G06T5/003 , G06T5/20 , G06T2207/20028 , G06T2207/20192
Abstract: A target pixel and surrounding pixels corresponding to the target pixel are obtained from a digitally represented image. A bilateral high pass filtering kernel is determined based at least in part upon the target pixel and the surrounding pixels. A high pass spatial filtering kernel is provided and multiplied with the high pass photometric filtering kernel to provide a bilateral high pass filtering kernel. The resulting bilateral high pass filtering kernel is thereafter applied to the target pixel and the surrounding pixels to provide a filtered pixel. When it is desirable to combine noise filtering capabilities with sharpening capabilities, the bilateral high pass filter of the present invention may be combined with a bilateral low pass filtering kernel to provide a combined noise reduction and edge sharpening filter. The present invention may be advantageously applied to a variety of devices, including cellular telephones that employ image sensing technology.
Abstract translation: 从数字表示的图像获得与目标像素对应的目标像素和周围像素。 至少部分地基于目标像素和周围像素来确定双边高通滤波核。 提供高通空间滤波核，并与高通光度滤波核相乘，以提供双边高通滤波核。 然后将所产生的双边高通滤波核应用于目标像素和周围像素以提供滤波像素。 当希望将噪声滤波能力与锐化能力相结合时，本发明的双向高通滤波器可与双边低通滤波核组合以提供组合降噪和边缘锐化滤波器。 本发明可以有利地应用于各种设备，包括采用图像感测技术的蜂窝电话。
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公开(公告)号：US08223796B2
公开(公告)日：2012-07-17
申请号：US12141358
申请日：2008-06-18
Applicant: Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
Inventor： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC: H04J3/16
CPC classification number: G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.
Abstract translation: 图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合为显示串行接口定义的协议的半双工双向串行链路和符合协议的单向串行链路 到为相机串行接口定义的兼容协议。 GMIC根据通过半双工双向串行链路的主机的协议接收数据包，并处理这些数据包。 GMIC根据协议将数据包通过单向串行链路发送到主机。 来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包，以在主机的内存中启动内存操作。 GMIC可以根据显示串行接口协议通过双向串行链路连接到显示器，并且可以根据相机串行接口通过单向串行链路和双向控制链路连接到相机，使得主机 通过GMIC间接控制显示和相机。
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Patent Agency Ranking
公开(公告)号：US08063957B2
公开(公告)日：2011-11-22
申请号：US11388937
申请日：2006-03-24
Applicant: Sergiu Goma , Milivoje Aleksic
Inventor： Sergiu Goma , Milivoje Aleksic
CPC classification number: H04N5/367
Abstract: A technique for processing at least one bad pixel occurring in an image sensing system is provided. Dynamic bad pixel detection is performed on a plurality of streaming pixels taking from at least one controlled image and value and coordinate information for each bad pixel is subsequently stored as stored bad pixel information. Thereafter, static bad pixel correction may be performed based on the stored bad pixel information. The stored bad pixel information may be verified based on histogram analysis performed on the plurality of streaming pixels. The technique for processing bad pixels in accordance with the present invention may be embodied in suitable circuitry or, more broadly, within devices incorporating image sensing systems.
Abstract translation: 提供了用于处理在图像感测系统中出现的至少一个不良像素的技术。 对从至少一个受控图像获取的多个流像素执行动态坏像素检测，并且随后将每个坏像素的坐标信息存储为存储的不良像素信息。 此后，可以基于存储的不良像素信息来执行静态坏像素校正。 可以基于对多个流式像素执行的直方图分析来验证存储的不良像素信息。 根据本发明的用于处理不良像素的技术可以体现在合适的电路中，或者更广泛地体现在包括图像感测系统的设备内。
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公开(公告)号：US20070222871A1
公开(公告)日：2007-09-27
申请号：US11388937
申请日：2006-03-24
Applicant: Sergiu Goma , Milivoje Aleksic
Inventor： Sergiu Goma , Milivoje Aleksic
IPC: H04N9/64
CPC classification number: H04N5/367
Abstract: A technique for processing at least one bad pixel occurring in an image sensing system is provided. Dynamic bad pixel detection is performed on a plurality of streaming pixels taking from at least one controlled image and value and coordinate information for each bad pixel is subsequently stored as stored bad pixel information. Thereafter, static bad pixel correction may be performed based on the stored bad pixel information. The stored bad pixel information may be verified based on histogram analysis performed on the plurality of streaming pixels. The technique for processing bad pixels in accordance with the present invention may be embodied in suitable circuitry or, more broadly, within devices incorporating image sensing systems.
Abstract translation: 提供了用于处理在图像感测系统中出现的至少一个不良像素的技术。 对从至少一个受控图像获取的多个流像素执行动态坏像素检测，并且随后将每个坏像素的坐标信息存储为存储的不良像素信息。 此后，可以基于存储的不良像素信息来执行静态坏像素校正。 可以基于对多个流式像素执行的直方图分析来验证存储的不良像素信息。 根据本发明的用于处理不良像素的技术可以体现在合适的电路中，或者更广泛地体现在包括图像感测系统的设备内。
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公开(公告)号：US20070079047A1
公开(公告)日：2007-04-05
申请号：US11536365
申请日：2006-09-28
Applicant: Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
Inventor： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC: G06F13/00
CPC classification number: G06F13/4018 , Y02D10/14 , Y02D10/151
Abstract: A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
Abstract translation: 缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。 数据字通过数据通道中的活动缓冲区进行定时。 通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。 这种方法允许其他非活动数据通道保持在功率节省状态。
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公开(公告)号：US20070073956A1
公开(公告)日：2007-03-29
申请号：US11237065
申请日：2005-09-28
Applicant: Sergiu Goma , Milivoje Aleksic
Inventor： Sergiu Goma , Milivoje Aleksic
IPC: G06F13/36
CPC classification number: G06F1/3203 , G06F1/3253 , G06F13/4282 , Y02D10/151
Abstract: A method of operating a shared bus comprises sending a wake-up signal on the shared bus. The wake-up signal comprises a sequence of signals, each signal of the sequence being one of a signal indicating the bus is free and a signal indicating the bus is busy. A microcontroller to effect this method is also contemplated. A wake-up device for a shared bus has a first latch to recognise a signal indicating one of said shared bus being free and said shared bus being busy and selectively output a recognition signal and a second latch to, after receipt of the recognition signal, recognise a signal indicating another of the shared bus being free and the shared bus being busy and selectively output a power-on signal. The latches may be D-type flip flops.
Abstract translation: 一种操作共享总线的方法包括在共享总线上发送唤醒信号。 唤醒信号包括一系列信号，序列的每个信号是指示总线空闲的信号之一，并且指示总线忙的信号。 也考虑了实现该方法的微控制器。 用于共享总线的唤醒装置具有第一锁存器，用于识别指示所述共享总线中的一个是空闲的信号，并且所述共享总线正忙，并且在接收到识别信号之后选择性地输出识别信号和第二锁存器， 识别指示共享总线中的另一个是空闲的信号，并且共享总线正在占用并选择性地输出通电信号。 锁存器可以是D型触发器。
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公开(公告)号：US08873581B2
公开(公告)日：2014-10-28
申请号：US13495518
申请日：2012-06-13
Applicant: Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
Inventor： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
CPC classification number: G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
Abstract translation: 图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合显示串行接口协议的半双工双向串行链路和符合相机的单向串行链路 串行接口协议 GMIC通过半双工双向串行链路从主机接收数据包，并处理这些数据包。 GMIC通过单向串行链路发送数据包。 来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包以启动主机存储器操作，并且可以通过双向串行链路连接到显示器，并且可以通过单向串行链路和允许主机的双向控制链路连接到摄像机 来控制显示器和相机。
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