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1.发明申请Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Compensation 有权非易失性存储器和位线对位线耦合补偿方法公开(公告)号：US20070297234A1
公开(公告)日：2007-12-27
申请号：US11848385
申请日：2007-08-31
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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2.发明授权Non-volatile memory and method with bit line to bit line coupled compensation 有权非易失性存储器和方式与位线到位线耦合补偿公开(公告)号：US07269069B2
公开(公告)日：2007-09-11
申请号：US11422034
申请日：2006-06-02
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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3.发明授权公开(公告)号：US06956770B2
公开(公告)日：2005-10-18
申请号：US10667223
申请日：2003-09-17
申请人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
发明人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
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4.发明申请Non-volatile memory and method with bit line compensation dependent on neighboring operating modes 有权具有位线补偿的非易失性存储器和方法取决于相邻的工作模式公开(公告)号：US20050057967A1
公开(公告)日：2005-03-17
申请号：US10667223
申请日：2003-09-17
申请人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
发明人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量作为电压偏移量加到编程中存储单元的位线。 电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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5.发明授权Non-volatile memory and method with bit line to bit line coupled compensation 有权非易失性存储器和方式与位线到位线耦合补偿公开(公告)号：US07532514B2
公开(公告)日：2009-05-12
申请号：US11848385
申请日：2007-08-31
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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6.发明申请Non-Volatile Memory and Method With Bit Line to Bit Line Coupled Compensation 有权非易失性存储器和具有位线到位线耦合补偿的方法公开(公告)号：US20060227614A1
公开(公告)日：2006-10-12
申请号：US11422034
申请日：2006-06-02
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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7.发明授权Non-volatile memory and method with bit line compensation dependent on neighboring operating modes 有权具有位线补偿的非易失性存储器和方法取决于相邻的工作模式公开(公告)号：US07215574B2
公开(公告)日：2007-05-08
申请号：US11250357
申请日：2005-10-13
申请人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
发明人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量作为电压偏移量加到编程中存储单元的位线。 电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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公开(公告)号：US07064980B2
公开(公告)日：2006-06-20
申请号：US10667222
申请日：2003-09-17
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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9.发明申请Non-volatile memory and method with bit line compensation dependent on neighboring operating modes 有权具有位线补偿的非易失性存储器和方法取决于相邻的工作模式公开(公告)号：US20060034121A1
公开(公告)日：2006-02-16
申请号：US11250357
申请日：2005-10-13
申请人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
发明人： Shahzad Khalid , Yan Li , Raul-Adrian Cernea , Mehrdad Mofidi
IPC分类号： G11C16/04
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量作为电压偏移量加到编程中存储单元的位线。 电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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公开(公告)号：US20050057965A1
公开(公告)日：2005-03-17
申请号：US10667222
申请日：2003-09-17
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译： 当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。 本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。 偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。 以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。
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