摘要:
Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
摘要:
In accordance with a method for reducing the likelihood of deadlock in a wireless communication system, user equipment may determine that user equipment has data to transmit. The data may correspond to a scheduled flow. The user equipment may determine that a scheduled grant corresponding to the scheduled flow is insufficient to transmit at least one protocol data unit. An insufficiency indicator may be transmitted to a scheduler at least once. The insufficiency indicator may include an indication that the scheduled grant is insufficient to transmit at least one protocol data unit.
摘要:
An apparatus and method for distributed data processing is described herein. A main processor programs a mini-processor to process an incoming data stream. The mini-processor is located in close proximity to hardware components operating on the input data stream. A copy engine is also provided for copying data from multiple protocol data units in a single copy operation.
摘要:
A single receiver can collect multiple protocol data units at one time originating from different sources. While it can be desirable for higher priority protocol data units to be processed, loss of data unit portions can cause confusion to the receiver. Therefore, even if a higher priority protocol data unit transfers to the receiver while a lower priority data unit is being processed, the lower priority unit can be completed before processing the higher priority unit; thus, there can be a lower likelihood of confusion among protocol data units.
摘要:
A single receiver can collect multiple protocol data units at one time originating from different sources. While it can be desirable for higher priority protocol data units to be processed, loss of data unit portions can cause confusion to the receiver. Therefore, even if a higher priority protocol data unit transfers to the receiver while a lower priority data unit is being processed, the lower priority unit can be completed before processing the higher priority unit; thus, there can be a lower likelihood of confusion among protocol data units.
摘要:
A single receiver can collect multiple protocol data units at one time originating from different sources. While it can be desirable for higher priority protocol data units to be processed, loss of data unit portions can cause confusion to the receiver. Therefore, even if a higher priority protocol data unit transfers to the receiver while a lower priority data unit is being processed, the lower priority unit can be completed before processing the higher priority unit; thus, there can be a lower likelihood of confusion among protocol data units.
摘要:
A single receiver can collect multiple protocol data units at one time originating from different sources. While it can be desirable for higher priority protocol data units to be processed, loss of data unit portions can cause confusion to the receiver. Therefore, even if a higher priority protocol data unit transfers to the receiver while a lower priority data unit is being processed, the lower priority unit can be completed before processing the higher priority unit; thus, there can be a lower likelihood of confusion among protocol data units.
摘要:
Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.
摘要:
Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
摘要:
Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.