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公开(公告)号：US08259890B2
公开(公告)日：2012-09-04
申请号：US12372741
申请日：2009-02-18
IPC分类号： H03D3/24
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/093 , H03L7/183 , H03L7/1976 , H03L2207/06
摘要： A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.
摘要翻译： 一种锁相环电路，包括：用于检测参考信号和反馈振荡信号之间的差以产生检测结果的操作电路，以及根据检测结果生成第一控制信号;辅助电路，用于产生第二 与第一控制信号异步的控制信号，以及耦合到操作电路和辅助电路的可控振荡器，用于根据第一控制信号和第二控制信号产生输出振荡信号，其中反馈振荡信号从 输出振荡信号。
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公开(公告)号：US20100208857A1
公开(公告)日：2010-08-19
申请号：US12372741
申请日：2009-02-18
IPC分类号： H03D3/24
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/093 , H03L7/183 , H03L7/1976 , H03L2207/06
摘要： A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.
摘要翻译： 一种锁相环电路，包括：用于检测参考信号和反馈振荡信号之间的差以产生检测结果的操作电路，以及根据检测结果生成第一控制信号;辅助电路，用于产生第二 与第一控制信号异步的控制信号，以及耦合到操作电路和辅助电路的可控振荡器，用于根据第一控制信号和第二控制信号产生输出振荡信号，其中反馈振荡信号从 输出振荡信号。
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公开(公告)号：US08644441B2
公开(公告)日：2014-02-04
申请号：US12209485
申请日：2008-09-12
申请人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
发明人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
IPC分类号： H03D3/24
CPC分类号： H03L7/1976 , H03L7/081
摘要： Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.
摘要翻译： 提供时钟发生器。 锁相环产生输出时钟，延迟线耦合到锁相环的输入端，并且调制单元将输入信号与恒定电平进行积分，以产生控制延迟线的调制信号，从而调制 锁相环的第一输入时钟，使得输出时钟的频率被锁定在期望的频率。
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公开(公告)号：US20090128201A1
公开(公告)日：2009-05-21
申请号：US12209485
申请日：2008-09-12
申请人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
发明人： Bo-Jiun Chen , Shang-Ping Chen , Ping-Ying Wang
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/081
摘要： Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.
摘要翻译： 提供时钟发生器。 锁相环产生输出时钟，延迟线耦合到锁相环的输入端，并且调制单元将输入信号与恒定电平进行积分，以产生控制延迟线的调制信号，从而调制 锁相环的第一输入时钟，使得输出时钟的频率被锁定在期望的频率。
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