公开(公告)号：US08259890B2

公开(公告)日：2012-09-04

申请号：US12372741

申请日：2009-02-18

申请人： Shang-Ping Chen ,  Ding-Shiuan Shen ,  Bo-Jiun Chen ,  Ping-Ying Wang

发明人： Shang-Ping Chen ,  Ding-Shiuan Shen ,  Bo-Jiun Chen ,  Ping-Ying Wang

IPC分类号： H03D3/24

CPC分类号： H03L7/0893 ,  H03L7/087 ,  H03L7/093 ,  H03L7/183 ,  H03L7/1976 ,  H03L2207/06

摘要： A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.

摘要翻译： 一种锁相环电路，包括：用于检测参考信号和反馈振荡信号之间的差以产生检测结果的操作电路，以及根据检测结果生成第一控制信号;辅助电路，用于产生第二 与第一控制信号异步的控制信号，以及耦合到操作电路和辅助电路的可控振荡器，用于根据第一控制信号和第二控制信号产生输出振荡信号，其中反馈振荡信号从 输出振荡信号。

公开(公告)号：US08644441B2

公开(公告)日：2014-02-04

申请号：US12209485

申请日：2008-09-12

申请人： Bo-Jiun Chen ,  Shang-Ping Chen ,  Ping-Ying Wang

发明人： Bo-Jiun Chen ,  Shang-Ping Chen ,  Ping-Ying Wang

IPC分类号： H03D3/24

CPC分类号： H03L7/1976 ,  H03L7/081

摘要： Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.

摘要翻译： 提供时钟发生器。 锁相环产生输出时钟，延迟线耦合到锁相环的输入端，并且调制单元将输入信号与恒定电平进行积分，以产生控制延迟线的调制信号，从而调制 锁相环的第一输入时钟，使得输出时钟的频率被锁定在期望的频率。

公开(公告)号：US20100208857A1

公开(公告)日：2010-08-19

申请号：US12372741

申请日：2009-02-18

申请人： Shang-Ping Chen ,  Ding-Shiuan Shen ,  Bo-Jiun Chen ,  Ping-Ying Wang

发明人： Shang-Ping Chen ,  Ding-Shiuan Shen ,  Bo-Jiun Chen ,  Ping-Ying Wang

IPC分类号： H03D3/24

CPC分类号： H03L7/0893 ,  H03L7/087 ,  H03L7/093 ,  H03L7/183 ,  H03L7/1976 ,  H03L2207/06

摘要： A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.

摘要翻译： 一种锁相环电路，包括：用于检测参考信号和反馈振荡信号之间的差以产生检测结果的操作电路，以及根据检测结果生成第一控制信号;辅助电路，用于产生第二 与第一控制信号异步的控制信号，以及耦合到操作电路和辅助电路的可控振荡器，用于根据第一控制信号和第二控制信号产生输出振荡信号，其中反馈振荡信号从 输出振荡信号。

公开(公告)号：US20090128201A1

公开(公告)日：2009-05-21

申请号：US12209485

申请日：2008-09-12

申请人： Bo-Jiun Chen ,  Shang-Ping Chen ,  Ping-Ying Wang

发明人： Bo-Jiun Chen ,  Shang-Ping Chen ,  Ping-Ying Wang

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/081

摘要： Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.

摘要翻译： 提供时钟发生器。 锁相环产生输出时钟，延迟线耦合到锁相环的输入端，并且调制单元将输入信号与恒定电平进行积分，以产生控制延迟线的调制信号，从而调制 锁相环的第一输入时钟，使得输出时钟的频率被锁定在期望的频率。

公开(公告)号：US08379787B2

公开(公告)日：2013-02-19

申请号：US11940486

申请日：2007-11-15

申请人： Shang-Ping Chen ,  Ping-Ying Wang

发明人： Shang-Ping Chen ,  Ping-Ying Wang

IPC分类号： H03D3/24

CPC分类号： H03B19/00 ,  H03L7/081 ,  H03L7/1976

摘要： Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.

摘要翻译： 扩频时钟发生器。 锁相环根据第一输入时钟和第二输入时钟产生输出时钟，延迟线耦合在第一输入时钟和锁相环之间。 调制单元提供调制信号以控制延迟线，从而调制第一输入时钟的相位，使得由锁相环产生的输出时钟的频率周期性地变化。

公开(公告)号：US08031025B2

公开(公告)日：2011-10-04

申请号：US12404384

申请日：2009-03-16

申请人： Ping-Ying Wang ,  Hsiang-Hui Chang

发明人： Ping-Ying Wang ,  Hsiang-Hui Chang

IPC分类号： H03L7/085 ,  H03C3/22

CPC分类号： H03L7/099 ,  H03L7/16

摘要： A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.

摘要翻译： 公开了一种混合模式PLL。 混合模式PLL包括数字Σ-Δ调制器，低通滤波器和数字控制振荡器。 数字Σ-Δ调制器接收分数位信号。 低通滤波器耦合到数字Σ-Δ调制器。 低通滤波器接收数字Σ-Δ调制器的输出信号并将输出信号转换为模拟控制信号。 数字控制振荡器包括动态耦合到低通滤波器并接收模拟控制信号的变容二极管。

公开(公告)号：US07893788B2

公开(公告)日：2011-02-22

申请号：US12369766

申请日：2009-02-12

申请人： Ping-Ying Wang ,  Hsiu-Ming Chang

发明人： Ping-Ying Wang ,  Hsiu-Ming Chang

IPC分类号： H03C3/06

CPC分类号： H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0975 ,  H03C3/20 ,  H03L7/087

摘要： A charge pump-based frequency modulator is provided. The charge pump-based frequency modulator comprises an analog phase correction path comprising a varactor and a charge pump. The varactor is coupled to an output of the charge pump-based frequency modulator. The charge pump is coupled to a node between the varactor and the output and receives a signal containing the modulated data.

摘要翻译： 提供基于电荷泵的频率调制器。 基于电荷泵的频率调制器包括包括变容二极管和电荷泵的模拟相位校正路径。 变容二极管耦合到基于电荷泵的频率调制器的输出。 电荷泵耦合到变容二极管和输出端之间的节点，并接收包含调制数据的信号。

公开(公告)号：US07791428B2

公开(公告)日：2010-09-07

申请号：US12235615

申请日：2008-09-23

申请人： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

发明人： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

IPC分类号： H03C3/02 ,  H03C3/08

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L2207/50

摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

摘要翻译： 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。

公开(公告)号：US07660376B2

公开(公告)日：2010-02-09

申请号：US11458388

申请日：2006-07-19

申请人： Ping-Ying Wang

发明人： Ping-Ying Wang

IPC分类号： H04L25/08

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/091 ,  H03L7/0992 ,  H03L7/0994

摘要： A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the feedback clock for generating a phase error signal according to the analog input signal and the feedback clock; a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; a numerically controlled oscillator (NCO) coupled to the loop filter for generating a first clock and an index signal according to the control signal; a delay locked loop (DLL) coupled to the NCO for receiving the first clock and generating a plurality of second clocks; and a multiplexer coupled to the NCO and the DLL for selecting one of the second clocks as the output clock according to the index signal.

摘要翻译： 用于产生锁定到模拟输入信号的输出时钟的时钟恢复电路包括：相位检测单元，用于接收模拟输入信号和反馈时钟，用于根据模拟输入信号和反馈时钟产生相位误差信号; 耦合到相位检测器的环路滤波器，用于对相位误差信号进行滤波并产生控制信号; 耦合到所述环路滤波器的数控振荡器（NCO），用于根据所述控制信号产生第一时钟和索引信号; 耦合到所述NCO的延迟锁定环（DLL），用于接收所述第一时钟并产生多个第二时钟; 以及耦合到所述NCO和所述DLL的多路复用器，用于根据所述索引信号选择所述第二时钟之一作为所述输出时钟。

公开(公告)号：US20090207901A1

公开(公告)日：2009-08-20

申请号：US12033018

申请日：2008-02-19

申请人： Meng-Ta Yang ,  Ping-Ying Wang

发明人： Meng-Ta Yang ,  Ping-Ying Wang

IPC分类号： H03H7/30 ,  H03K5/159

CPC分类号： H03L7/0812 ,  H03L7/0814 ,  H03L7/0818

摘要： A delay circuit includes a first reference delay module, a second reference delay module and a first delay module. The first reference delay module delays a reference signal and generates a first reference delayed signal, and the second reference delay module delays the reference signal and generates a second reference delayed signal according to a reference control signal and the first reference delayed signal. The first delay module delays a first input signal and generates a first output signal according to a first control signal and the second reference delayed signal.

摘要翻译： 延迟电路包括第一参考延迟模块，第二参考延迟模块和第一延迟模块。 第一参考延迟模块延迟参考信号并产生第一参考延迟信号，并且第二参考延迟模块延迟参考信号，并根据参考控制信号和第一参考延迟信号产生第二参考延迟信号。 第一延迟模块延迟第一输入信号并根据第一控制信号和第二参考延迟信号产生第一输出信号。