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111 条记录 (耗时 0.024 秒)

    Interleaver and de-interleaver for iterative code systems
    1.
    发明授权
    Interleaver and de-interleaver for iterative code systems 失效
    用于迭代代码系统的交织器和解交织器

    公开(公告)号：US08205123B2

    公开(公告)日：2012-06-19

    申请号：US12315601

    申请日：2008-12-04

    申请人： Shaohua Yang ,  Changyou Xu ,  Weijun Tan ,  Ching-Fu Wu ,  Yuan Xing Lee

    发明人： Shaohua Yang ,  Changyou Xu ,  Weijun Tan ,  Ching-Fu Wu ,  Yuan Xing Lee

    IPC分类号： H03M13/27

    CPC分类号： G06F12/0207 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0065

    摘要： In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.

    摘要翻译： 在示例性实施例中，描述了用于迭代代码系统的偏斜交错功能。 倾斜交错功能提供了一个倾斜的行和列存储器分区以及用于重新排列从例如第一通道检测器读取的数据样本的分层结构。 诸如基于低密度奇偶校验码（LDPC）的迭代解码器的迭代解码器可以在执行数据的迭代解码之前采用去除来自交错存储器分区的数据的元素， 在将解码的样本传递到解交织器之前，将信息偏移。 解交织器在将解码的数据样本传递到例如第二信道检测器之前，根据交织器功能的反向重新排列迭代解码的数据样本。

    Interleaver and de-interleaver for iterative code systems
    2.
    发明申请
    Interleaver and de-interleaver for iterative code systems 失效
    用于迭代代码系统的交织器和解交织器

    公开(公告)号：US20100146229A1

    公开(公告)日：2010-06-10

    申请号：US12315601

    申请日：2008-12-04

    申请人： Shaohua Yang ,  Changyou Xu ,  Weijun Tan ,  Ching-Fu Wu ,  Yuan Xing Lee

    发明人： Shaohua Yang ,  Changyou Xu ,  Weijun Tan ,  Ching-Fu Wu ,  Yuan Xing Lee

    IPC分类号： G06F12/02 ,  G11C29/04 ,  G06F11/07

    CPC分类号： G06F12/0207 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0065

    摘要： In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.

    摘要翻译： 在示例性实施例中，描述了用于迭代代码系统的偏斜交错功能。 倾斜交错功能提供了一个倾斜的行和列存储器分区以及用于重新排列从例如第一通道检测器读取的数据样本的分层结构。 诸如基于低密度奇偶校验码（LDPC）的迭代解码器的迭代解码器可以在执行数据的迭代解码之前采用去除来自交错存储器分区的数据的元素， 在将解码的样本传递到解交织器之前，将信息偏移。 解交织器在将解码的数据样本传递到例如第二信道检测器之前，根据交织器功能的反向重新排列迭代解码的数据样本。

    Systems and Methods for Hard Decision Assisted Decoding
    5.
    发明申请
    Systems and Methods for Hard Decision Assisted Decoding 有权
    硬判决辅助解码的系统和方法

    公开(公告)号：US20100275096A1

    公开(公告)日：2010-10-28

    申请号：US12430927

    申请日：2009-04-28

    申请人： Hao Zhong ,  Shaohua Yang ,  Weijun Tan ,  Changyou Xu ,  Yuan Xing Lee

    发明人： Hao Zhong ,  Shaohua Yang ,  Weijun Tan ,  Changyou Xu ,  Yuan Xing Lee

    IPC分类号： H03M13/00 ,  G06F11/00

    CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/3715 ,  H03M13/6331

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，公开了一种包括具有数据检测器和软判决解码器的处理环路电路的数据处理系统。 数据检测器提供检测输出，软判决解码器将软解码算法应用于检测输出的导数，以产生软决策输出和第一硬决策输出。 该系统还包括排队缓冲器和硬判决解码器。 排队缓冲器可操作以存储软判决输出，并且硬判决解码器访问软决策输出并应用硬解码算法以产生第二硬决策输出。 如果软判决解码器和硬判决解码器不能收敛，则数据检测器可操作以对软决策输出的导数执行数据检测

    Systems and methods for hard decision assisted decoding
    6.
    发明授权
    Systems and methods for hard decision assisted decoding 有权
    硬判决辅助解码的系统和方法

    公开(公告)号：US08443267B2

    公开(公告)日：2013-05-14

    申请号：US12430927

    申请日：2009-04-28

    申请人： Hao Zhong ,  Shaohua Yang ,  Weijun Tan ,  Changyou Xu ,  Yuan Xing Lee

    发明人： Hao Zhong ,  Shaohua Yang ,  Weijun Tan ,  Changyou Xu ,  Yuan Xing Lee

    IPC分类号： G06F11/00

    CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/3715 ,  H03M13/6331

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，公开了一种包括具有数据检测器和软判决解码器的处理环路电路的数据处理系统。 数据检测器提供检测输出，软判决解码器将软解码算法应用于检测输出的导数，以产生软决策输出和第一硬决策输出。 该系统还包括排队缓冲器和硬判决解码器。 排队缓冲器可操作以存储软判决输出，并且硬判决解码器访问软决策输出并应用硬解码算法以产生第二硬决策输出。 如果软判决解码器和硬判决解码器不能收敛，则数据检测器可操作以对软决策输出的导数执行数据检测。

    Systems and Methods for Stepped Data Retry in a Storage System
    9.
    发明申请
    Systems and Methods for Stepped Data Retry in a Storage System 有权
    存储系统中步进数据重试的系统和方法

    公开(公告)号：US20110060973A1

    公开(公告)日：2011-03-10

    申请号：US12556145

    申请日：2009-09-09

    申请人： Shaohua Yang ,  Weijun Tan ,  Yuan Xing Lee

    发明人： Shaohua Yang ,  Weijun Tan ,  Yuan Xing Lee

    IPC分类号： G06F11/07 ,  G06F12/02

    CPC分类号： G11B20/1879 ,  G11B20/10527 ,  G11B2020/1062 ,  G11B2020/10694 ,  G11B2020/10851 ,  G11B2020/183 ,  G11B2220/2516

    摘要： Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time.

    摘要翻译： 本发明的各种实施例提供了用于数据处理重试的系统和方法。 作为示例，讨论了包括阶梯式擦除窗口寄存器和擦除标志设置电路的数据处理重试电路。 阶梯式擦除窗口寄存器包括：擦除标志位置，擦除标志长度和步长。 擦除标志设置电路可操作来断言在擦除标志位置开始的第一擦除标志，并且在第一时间具有擦除标志长度。 此外，擦除标志设置电路可操作来断言从擦除标志位置开始的第二擦除标志加上步长，并且第二次具有擦除标志长度。