Correcting errors in miscorrected codewords using list decoding
    3.
    发明授权
    Correcting errors in miscorrected codewords using list decoding 有权
    使用列表解码校正错误码字中的错误

    公开(公告)号:US08898539B2

    公开(公告)日:2014-11-25

    申请号:US13611158

    申请日:2012-09-12

    IPC分类号: H03M13/00

    摘要: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

    摘要翻译: 通信系统的接收路径包括纠错解码器,错误检测解码器和码字调节器。 误差校正解码器对接收的码字进行纠错解码,以生成有效的码字。 错误检测解码器对有效码字执行错误检测解码,以确定有效码字是否是发送的正确码字。 如果有效码字不是正确的码字,则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。 错误检测解码器对经调整的有效码字执行错误检测解码,以确定调整后的有效码字是否为正确码字。 当纠错解码器产生不正确的有效码字时,调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。

    CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING
    4.
    发明申请
    CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING 有权
    使用列表解码纠正错误的代码中的错误

    公开(公告)号:US20140075264A1

    公开(公告)日:2014-03-13

    申请号:US13611158

    申请日:2012-09-12

    IPC分类号: H03M13/05 H03M13/13

    摘要: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

    摘要翻译: 通信系统的接收路径包括纠错解码器,错误检测解码器和码字调节器。 误差校正解码器对接收的码字进行纠错解码,以生成有效的码字。 错误检测解码器对有效码字执行错误检测解码,以确定有效码字是否是发送的正确码字。 如果有效码字不是正确的码字,则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。 错误检测解码器对经调整的有效码字执行错误检测解码,以确定调整后的有效码字是否为正确码字。 当纠错解码器产生不正确的有效码字时,调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。

    Systems and methods for non-binary decoding
    7.
    发明授权
    Systems and methods for non-binary decoding 有权
    用于非二进制解码的系统和方法

    公开(公告)号:US08560929B2

    公开(公告)日:2013-10-15

    申请号:US13167764

    申请日:2011-06-24

    IPC分类号: H03M13/00

    摘要: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 公开了一种数据处理电路,其包括:数据检测器电路,第一符号约束布置电路和第二符号约束布置电路。 数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合,以产生包括多个非二进制符号的检测输出。 第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。 来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。 第二符号约束布置电路可操作以接收第二输入数据集并且根据第二布置算法重排第二数据输入以产生解码数据集。 用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

    Systems and Methods for Non-Binary Decoding
    8.
    发明申请
    Systems and Methods for Non-Binary Decoding 有权
    非二进制解码的系统和方法

    公开(公告)号:US20120331370A1

    公开(公告)日:2012-12-27

    申请号:US13167764

    申请日:2011-06-24

    IPC分类号: G06F11/08

    摘要: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 公开了一种数据处理电路,其包括:数据检测器电路,第一符号约束布置电路和第二符号约束布置电路。 数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合,以产生包括多个非二进制符号的检测输出。 第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。 来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。 第二符号约束排列电路可操作以接收第二输入数据集并且根据第二布置算法重新布置第二数据输入以产生解码的数据集。 用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

    Systems and methods for power measurement in a data processing system
    10.
    发明授权
    Systems and methods for power measurement in a data processing system 有权
    数据处理系统中功率测量的系统和方法

    公开(公告)号:US08856575B2

    公开(公告)日:2014-10-07

    申请号:US13284684

    申请日:2011-10-28

    IPC分类号: G06F1/00 G06F11/30 G06F1/30

    CPC分类号: G06F11/3062 G06F1/30

    摘要: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a power usage control circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a data set derived from the detected output to yield a decoded output. The power usage control circuit is operable to force a defined number of global iterations applied to the data input by the data detector circuit and the data decoder circuit regardless of convergence of the data decode algorithm.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例,公开了一种数据处理电路,其包括:数据检测器电路,数据解码器电路和电力使用控制电路。 数据检测器电路可操作以将数据检测算法应用于数据输入以产生检测到的输出。 数据解码器电路可操作以将数据解码算法应用于从检测到的输出导出的数据集,以产生解码输出。 功率使用控制电路可操作以强制对数据检测器电路和数据解码器电路输入的数据施加的定义数量的全局迭代,而与数据解码算法的收敛无关。