公开(公告)号：US06522574B2

公开(公告)日：2003-02-18

申请号：US09964218

申请日：2001-09-25

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C11/15 ,  H01L27/222

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

公开(公告)号：US06791856B2

公开(公告)日：2004-09-14

申请号：US10327581

申请日：2002-12-20

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C506

CPC分类号： G11C11/16 ,  G11C11/15 ,  H01L27/222

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

公开(公告)号：US06756240B2

公开(公告)日：2004-06-29

申请号：US10614622

申请日：2003-07-07

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： H01L2100

CPC分类号： G11C11/16 ,  G11C11/15 ,  H01L27/222

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

摘要翻译： 公开了在不显着降低存储器的封装密度的情况下产生增加的写入裕度和写入选择性的MRAM架构。 磁阻位的主轴相对于数字线的轴线偏移，以从沿着磁阻位的长轴延伸的数字线电流产生磁场分量。

公开(公告)号：US06992918B2

公开(公告)日：2006-01-31

申请号：US10614709

申请日：2003-07-07

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/15 ,  H01L27/222

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

公开(公告)号：US06424564B1

公开(公告)日：2002-07-23

申请号：US09964217

申请日：2001-09-26

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C1100

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

公开(公告)号：US06424561B1

公开(公告)日：2002-07-23

申请号：US09618504

申请日：2000-07-18

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C11/15 ,  H01L27/222

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

摘要翻译： 公开了在不显着降低存储器的封装密度的情况下产生增加的写入裕度和写入选择性的MRAM架构。 磁阻位的主轴相对于数字线的轴线偏移，以从沿着磁阻位的长轴延伸的数字线电流产生磁场分量。

公开(公告)号：US06623987B2

公开(公告)日：2003-09-23

申请号：US10057162

申请日：2002-01-24

申请人： Harry Liu ,  Lonny Berg ,  William L. Larson ,  Shaoping Li ,  Theodore Zhu ,  Joel Drewes

发明人： Harry Liu ,  Lonny Berg ,  William L. Larson ,  Shaoping Li ,  Theodore Zhu ,  Joel Drewes

IPC分类号： G11C1115

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/08 ,  H01L43/12

摘要： A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

公开(公告)号：US06392922B1

公开(公告)日：2002-05-21

申请号：US09638419

申请日：2000-08-14

申请人： Harry Liu ,  Lonny Berg ,  William L. Larson ,  Shaoping Li ,  Theodore Zhu ,  Joel Drewes

发明人： Harry Liu ,  Lonny Berg ,  William L. Larson ,  Shaoping Li ,  Theodore Zhu ,  Joel Drewes

IPC分类号： H01L2982

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/08 ,  H01L43/12

摘要： A passivated magneto-resistive bit structure is disclosed in which surfaces subject to oxidation or corrosion are protected. In one embodiment a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

摘要翻译： 公开了钝化的磁阻钻头结构，其中受到氧化或腐蚀的表面被保护。 在一个实施例中，位结构通过蚀刻停止阻挡材料被封装。 在另一个实施例中，蚀刻停止阻挡材料保护位结构的顶部并且电介质间隔件保护侧壁。

公开(公告)号：US07427514B2

公开(公告)日：2008-09-23

申请号：US10646103

申请日：2003-08-22

申请人： Harry Liu ,  Lonny Berg ,  William L. Larson ,  Shaoping Li ,  Theodore Zhu ,  Joel Drewes

发明人： Harry Liu ,  Lonny Berg ,  William L. Larson ,  Shaoping Li ,  Theodore Zhu ,  Joel Drewes

IPC分类号： G11C11/00 ,  H01L41/22 ,  H01L45/00

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/08 ,  H01L43/12

摘要： A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

摘要翻译： 公开了钝化的磁阻钻头结构，其中受保护的氧化或腐蚀的表面。 在一个实施例中，位结构通过蚀刻停止阻挡材料被封装。 在另一个实施例中，蚀刻停止阻挡材料保护位结构的顶部并且电介质间隔件保护侧壁。

公开(公告)号：US5907784A

公开(公告)日：1999-05-25

申请号：US799833

申请日：1997-02-13

申请人： William L. Larson

发明人： William L. Larson

IPC分类号： A61K38/12 ,  C07K7/62 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L29/49 ,  H01L21/4763

CPC分类号： H01L29/4975 ,  C07K7/62 ,  H01L21/28097 ,  H01L2924/0002

摘要： A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

摘要翻译： 一种形成用于MOS型半导体器件的多层硅化物栅极结构的方法，包括以下步骤：首先提供衬底，然后在衬底上沉积栅氧化层，然后沉积第一难熔金属硅化物层，其具有第一 在第一沉积难熔金属硅化物层上沉积第二难熔金属硅化物层，该第二难熔金属硅化物层具有与第一沉积物不同的第二固态测量法。