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公开(公告)号:US20240355287A1
公开(公告)日:2024-10-24
申请号:US18683526
申请日:2021-09-30
IPC分类号: G09G3/3233
CPC分类号: G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/06 , G09G2320/0247 , G09G2330/02
摘要: When a current-driven display device with an internal compensation method operates in a pause driving mode, a non-light emission period according to a light emission duty is provided in both a refresh frame period and a non-refresh frame period, and an on-bias applying period for applying on-bias to a drive transistor in a pixel circuit is provided in both the non-light emission periods. In the non-light emission period in the refresh frame period, an on-bias applying period is provided in a period from when data writing with threshold compensation is performed to when the light emission period starts. Thus, even when the light emission duty is low, the difference in the stress state of the drive transistor between the refresh frame period and the non-refresh frame period is reduced.
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公开(公告)号:US20240274090A1
公开(公告)日:2024-08-15
申请号:US18566949
申请日:2021-07-05
发明人: Kaoru YAMAMOTO
IPC分类号: G09G3/3275 , G09G3/3266
CPC分类号: G09G3/3275 , G09G3/3266 , G09G2300/043 , G09G2310/0278 , G09G2310/0286 , G09G2310/08 , G09G2330/021
摘要: To realize frame narrowing of a display device that uses a display element driven by a current. A second scanning signal line drive circuit configured to drive second scanning signal lines each connected to a control terminal of a writing control transistor is constituted by a shift register composed of unit circuits equal in number to half a number of the second scanning signal lines. Each of the unit circuits included in the shift register collectively drives two of the second scanning signal lines adjacent to each other. In a period during which a power supply control transistor and a light emission control transistor are maintained in an off state and the writing control transistor is maintained in an on state in first and second pixel circuits connected to the two second scanning signal lines adjacent to each other, a threshold voltage compensation transistor and an initialization transistor in the first pixel circuit and a threshold voltage compensation transistor and an initialization transistor in the second pixel circuit are sequentially set to an on state for a predetermined period each.
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