公开(公告)号：US20210327911A1

公开(公告)日：2021-10-21

申请号：US17224166

申请日：2021-04-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20200303425A1

公开(公告)日：2020-09-24

申请号：US16820900

申请日：2020-03-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Masamitsu YAMANAKA ,  Teruyuki UEDA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/24 ,  H01L29/786 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1333

Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.

公开(公告)号：US20190081077A1

公开(公告)日：2019-03-14

申请号：US16084568

申请日：2017-03-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hajime IMAI ,  Hisao OCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Toshikatsu ITOH ,  Teruyuki UEDA ,  Ryosuke GUNJI ,  Kengo HARA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

Abstract: An active matrix substrate includes a substrate, a TFT-containing layer which is supported on the substrate, and which includes a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes of the TFT, a metal wiring layer which is supported on the substrate and has a thickness of 400 nm or more, and an inorganic insulating layer which is thinner than the metal wiring layer, and is arranged on a substrate side of the metal wiring layer and is in contact with a lower surface of the metal wiring layer. The metal wiring layer has tensile stress and the inorganic insulating layer has compressive stress, and a ratio Sb/Sa of an absolute value Sb of a stress value of the inorganic insulating layer to an absolute value Sa of a stress value of the metal wiring layer is 0.6 or more and 1.7 or less.

公开(公告)号：US20230100273A1

公开(公告)日：2023-03-30

申请号：US18076433

申请日：2022-12-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  H01L27/32

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

公开(公告)号：US20220208793A1

公开(公告)日：2022-06-30

申请号：US17559045

申请日：2021-12-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Hitoshi TAKAHATA ,  Tetsuo KIKUCHI ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Masahiko SUZUKI ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.

公开(公告)号：US20210305280A1

公开(公告)日：2021-09-30

申请号：US16497505

申请日：2018-03-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC: H01L27/12 ,  G02F1/1362

Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.

公开(公告)号：US20210294138A1

公开(公告)日：2021-09-23

申请号：US16336483

申请日：2017-09-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Toshikatsu ITOH ,  Teruyuki UEDA ,  Setsuji NISHIMIYA ,  Kengo HARA

IPC: G02F1/1368 ,  H01L27/12

Abstract: A pixel area in the active matrix substrate 100 includes a thin film transistor 101 that has an oxide semiconductor layer 7, an inorganic insulating layer 11 and an organic insulating layer 12 that cover a thin film transistor, a common electrode 15, a dielectric layer 17 that primarily contains silicon nitride, and a pixel electrode 19. The inorganic insulating layer has a multi-layered structure that includes a silicon oxide layer and a silicon nitride layer. A pixel electrode 10 is brought into contact with a drain electrode 9 within a pixel contact hole. The pixel contact hole is configured with a first opening portion, a second opening portion, and a third opening portion that are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. A flank surface of the first opening portion and a flank surface of the second opening portion are aligned. The flank surface of the second opening portion includes a first portion 121 that is inclined at a first angle θ1 with respect to a substrate, a second portion 122 that is positioned above the first portion and is inclined at a second angle θ2 that is greater than the first angle, and a border 120 that is positioned between the first portion and the second portion and of which an inclination angle with respect to the substrate discontinuously changes.

公开(公告)号：US20200264485A1

公开(公告)日：2020-08-20

申请号：US16788423

申请日：2020-02-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Setsuji NISHIMIYA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1333

Abstract: An active matrix substrate 10 includes: switching elements 120 that are connected with gate lines and data lines provided on a substrate; pixel electrodes 130 that are connected with the switching elements 120; counter electrodes 140 that overlap with the pixel electrodes 130 when viewed in a plan view; a flattening film 154; and lines 142. The flattening film 154 covers the switching elements 120, and first contact holes CH1 that pass through the flattening film 154 are formed at positions that overlap with the lines 142 when viewed in a plan view. The pixel electrodes 130 and the counter electrodes 140 are arranged so that each of the same partially covers the flattening film 154. The line 142 and the counter electrode 140 are connected with each other in the first contact hole CH1.

公开(公告)号：US20190326443A1

公开(公告)日：2019-10-24

申请号：US16336481

申请日：2017-09-21

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hajime IMAI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Tohru DAITOH ,  Toshikatsu ITOH

IPC: H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L29/66 ,  H01L27/12 ,  G02F1/1345 ,  G02F1/1368 ,  G02F1/1343

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is arranged nearer to the gate insulating layer than the second oxide semiconductor layer.

公开(公告)号：US20190103421A1

公开(公告)日：2019-04-04

申请号：US16132509

申请日：2018-09-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1333 ,  G06F3/041

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.