公开(公告)号：US20210013238A1

公开(公告)日：2021-01-14

申请号：US16919422

申请日：2020-07-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Masamitsu YAMANAKA ,  Hitoshi TAKAHATA ,  Hajime IMAI ,  Tohru DAITOH

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

Abstract: An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate.

公开(公告)号：US20200150472A1

公开(公告)日：2020-05-14

申请号：US16683726

申请日：2019-11-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Masamitsu YAMANAKA ,  Hitoshi TAKAHATA

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1333

Abstract: A substrate includes thin film transistors, each of which includes: an upper gate electrode formed of a first conductive film and continuous with one of gate lines; a source electrode formed of a second conductive film and continuous with one of source lines; a channel region formed of a portion of a semiconductor film over which an upper gate insulating film is disposed and overlapping the upper gate electrode; a source region formed of a portion of the semiconductor film and continuous with the channel region, and a drain region formed of a portion of the semiconductor film and continuous with the channel region on an opposite side of the channel region from the source region. The source electrode connects the source line and the source region through a first contact hole in an interlayer insulating film disposed over the first conductive film and containing a photosensitive material.

公开(公告)号：US20190280126A1

公开(公告)日：2019-09-12

申请号：US16293900

申请日：2019-03-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Tohru DAITOH ,  Hajime IMAI ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  G02F1/1368

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.

公开(公告)号：US20220005838A1

公开(公告)日：2022-01-06

申请号：US17364938

申请日：2021-07-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Masamitsu YAMANAKA ,  Yoshimasa CHIKAMA

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on a part of the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, the oxide semiconductor layer, in a first region covered with the gate electrode with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode, has a layered structure including a lower oxide semiconductor film and an upper oxide semiconductor film throughout and a mobility of the upper oxide semiconductor film is higher than a mobility of the lower oxide semiconductor film, and in the second TFT, in at least a part of a first region of the oxide semiconductor layer, of the lower oxide semiconductor film and the upper oxide semiconductor film, one oxide semiconductor film is provided, and another oxide semiconductor film is not provided.

公开(公告)号：US20200303425A1

公开(公告)日：2020-09-24

申请号：US16820900

申请日：2020-03-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Masamitsu YAMANAKA ,  Teruyuki UEDA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/24 ,  H01L29/786 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1333

Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.

公开(公告)号：US20220317532A1

公开(公告)日：2022-10-06

申请号：US17708121

申请日：2022-03-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshimasa CHIKAMA ,  Masamitsu YAMANAKA

IPC: G02F1/1362 ,  G02F1/1368

Abstract: A first substrate of a liquid crystal display device includes a plurality of gate wiring lines, a plurality of source wiring lines, a thin film transistor (TFT) provided in each of the pixels, a pixel electrode formed of a transparent conductive material and electrically connected to the TFT, a reflective electrode including a portion positioned in a reflective region, and a terminal portion disposed in a non-display region. The pixel electrode is formed in an upper layer above the reflective electrode, and the reflective electrode is not in contact with the pixel electrode. The terminal portion includes at least one of a first conductive layer formed in a same layer as that of the gate wiring lines and a second conductive layer formed in a same layer as that of the source wiring lines, and a third conductive layer formed in a same layer as that of the pixel electrode, and does not include a conductive layer formed in a same layer as that of the reflective electrode.

公开(公告)号：US20200264485A1

公开(公告)日：2020-08-20

申请号：US16788423

申请日：2020-02-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Setsuji NISHIMIYA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1333

Abstract: An active matrix substrate 10 includes: switching elements 120 that are connected with gate lines and data lines provided on a substrate; pixel electrodes 130 that are connected with the switching elements 120; counter electrodes 140 that overlap with the pixel electrodes 130 when viewed in a plan view; a flattening film 154; and lines 142. The flattening film 154 covers the switching elements 120, and first contact holes CH1 that pass through the flattening film 154 are formed at positions that overlap with the lines 142 when viewed in a plan view. The pixel electrodes 130 and the counter electrodes 140 are arranged so that each of the same partially covers the flattening film 154. The line 142 and the counter electrode 140 are connected with each other in the first contact hole CH1.

公开(公告)号：US20200287054A1

公开(公告)日：2020-09-10

申请号：US16808463

申请日：2020-03-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Yoshimasa CHIKAMA ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode that are electrically connected to the semiconductor layer, wherein the semiconductor layer has a stacked layer structure including a first oxide semiconductor layer including In, Ga, Zn, and Sn, and a second oxide semiconductor layer including In, Ga, Zn, and Sn, having a lower mobility than the first oxide semiconductor layer, and disposed on the first oxide semiconductor layer so as to be in direct contact with the first oxide semiconductor layer, the first and the second oxide semiconductor layers are amorphous, and a Sn atomic ratio R1 relative to all metal elements in the first oxide semiconductor layer and a Sn atomic ratio R2 relative to all metal elements in the second oxide semiconductor layer satisfy 0.8×R1≤R2≤1.2×R1.

公开(公告)号：US20200073189A1

公开(公告)日：2020-03-05

申请号：US16548886

申请日：2019-08-23

Applicant: Sharp Kabushiki Kaisha

Inventor： Hitoshi TAKAHATA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Kengo HARA ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Yoshihito HARA

IPC: G02F1/1362 ,  H01L27/12 ,  H01L27/32

Abstract: [Object]To provide an active matrix substrate (1) that includes an organic insulating film (OIL) and first source layers (FSL2 to FSL4) and second source layers (SSL1 to SSL3), which constitute two-layer wiring lines, and that is produced with a high yield.[Solution]In an active matrix substrate (1), of the first source layers (FSL2 to FSL4) and the second source layers (SSL1 to SSL3), the second source layers (SSL1 to SSL3) arranged further from the substrate (2) are in contact with an organic insulating film (OIL) with a second inorganic insulating film (SINOIL) interposed therebetween.

公开(公告)号：US20200043955A1

公开(公告)日：2020-02-06

申请号：US16515057

申请日：2019-07-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362

Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.