公开(公告)号：US20200135132A1

公开(公告)日：2020-04-30

申请号：US16659681

申请日：2019-10-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Kohhei TANAKA ,  Takuya WATANABE ,  Yasuaki IWASE

IPC: G09G3/36

Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

公开(公告)号：US20170140729A1

公开(公告)日：2017-05-18

申请号：US15322802

申请日：2015-06-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Toshitsugu SUEKI ,  Yasuaki IWASE ,  Takuya WATANABE ,  Akira TAGAWA ,  Kengo HARA

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  G11C19/287

Abstract: An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

公开(公告)号：US20190279589A1

公开(公告)日：2019-09-12

申请号：US16291049

申请日：2019-03-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Takatsugu KUSUMI ,  Takuya WATANABE ,  Akira TAGAWA ,  Yasuaki IWASE ,  Yohei TAKEUCHI

IPC: G09G3/36

Abstract: The present application discloses a scanning signal line drive circuit capable of reducing power consumption and narrowing a picture-frame while ensuring high-speed scanning for image display. First and second gate drivers 410, 420 are arranged to face each other via a display unit 500. Based on a DC buffer method, odd-numbered gate lines are driven by the first gate driver 410 while even-numbered gate bus lines are driven by the second gate driver 420, and when each gate bus line GLi is to be brought into a non-selected state, charges are released from both ends thereof. For this purpose, for example, the end portion of the odd-numbered gate bus line on the first gate driver side is connected to a buffer made up of the activation and inactivation transistors M10, M13L, and the end portion of the odd-numbered gate bus line on the second gate driver side is connected to the inactivation auxiliary transistor M13R.

公开(公告)号：US20220254814A1

公开(公告)日：2022-08-11

申请号：US17591042

申请日：2022-02-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Jun NISHIMURA ,  Akira TAGAWA ,  Yohei TAKEUCHI ,  Yasuaki IWASE

IPC: H01L27/12

Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.

公开(公告)号：US20200074907A1

公开(公告)日：2020-03-05

申请号：US16551768

申请日：2019-08-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Akira TAGAWA ,  Yasuaki IWASE ,  Jun NISHIMURA ,  Takuya WATANABE ,  Yohei TAKEUCHI

IPC: G09G3/20

Abstract: [Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation.[Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.

公开(公告)号：US20170285375A1

公开(公告)日：2017-10-05

申请号：US15511427

申请日：2015-09-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Yasuaki IWASE ,  Takuya WATANABE

IPC: G02F1/133 ,  G11C19/28 ,  G09G3/20 ,  G11C8/04 ,  G09G3/36

CPC classification number: G02F1/133 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C8/04 ,  G11C19/28

Abstract: The present invention provides a monolithic gate driver that includes fewer elements than in conventional configurations. A plurality of stages included in a shift register are divided into a plurality of stage circuit groups, where each stage circuit group includes the stage circuits of P adjacent stages (two stages, for example). Each stage circuit group includes a stabilization node and a stabilization node controller that controls the voltage of the stabilization node. The stabilization node controller includes: thin-film transistors in which the gate terminals thereof are connected to output control nodes, the drain terminals thereof are connected to the stabilization node, and the source terminals thereof are connected to an input terminal for a DC supply voltage; and a thin-film transistor for changing the voltage of the stabilization node to a high level.

公开(公告)号：US20210125575A1

公开(公告)日：2021-04-29

申请号：US17064677

申请日：2020-10-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Jun NISHIMURA ,  Takuya WATANABE ,  Akira TAGAWA ,  Yasuaki IWASE ,  Yohei TAKEUCHI

IPC: G09G3/36 ,  G09G3/20

Abstract: A demultiplexing circuit provided in a display device including an active matrix substrate includes demultiplexers respectively corresponding to sets of source bus line groups obtained by dividing source bus lines in the active matrix substrate into groups with two or more source bus lines making up one set, and input terminals respectively corresponding to the demultiplexers. Each demultiplexer includes two or more main switching elements respectively corresponding to two or more source bus lines of the corresponding set, and two or more sub-switching elements respectively connected in parallel with the two or more main switching elements, the input terminals are respectively connected to the two or more source bus lines via the two or more main switching elements, and each of the two or more sub-switching elements is controlled to be turned off at a time later than a time when the corresponding main switching element is turned off.

公开(公告)号：US20210035519A1

公开(公告)日：2021-02-04

申请号：US16935238

申请日：2020-07-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Akira TAGAWA ,  Takuya WATANABE ,  Jun NISHIMURA ,  Yasuaki IWASE ,  Yohei TAKEUCHI

IPC: G09G3/36

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

公开(公告)号：US20190325838A1

公开(公告)日：2019-10-24

申请号：US16390033

申请日：2019-04-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Akira TAGAWA ,  Yasuaki IWASE ,  Takuya WATANABE ,  Takatsugu KUSUMI ,  Yohei TAKEUCHI

IPC: G09G3/36

Abstract: There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.

公开(公告)号：US20190172843A1

公开(公告)日：2019-06-06

申请号：US16081455

申请日：2017-02-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Tokuo YOSHIDA ,  Takuya WATANABE ,  Akira TAGAWA ,  Yasuaki IWASE ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  G09G3/36 ,  G11C19/28

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.