公开(公告)号：US07668010B2

公开(公告)日：2010-02-23

申请号：US12038612

申请日：2008-02-27

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07889556B2

公开(公告)日：2011-02-15

申请号：US12690582

申请日：2010-01-20

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US20100120210A1

公开(公告)日：2010-05-13

申请号：US12690582

申请日：2010-01-20

申请人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07971177B2

公开(公告)日：2011-06-28

申请号：US12182352

申请日：2008-07-30

申请人： Shaw Hung Ku ,  Chia Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Chia Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/78

摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

摘要翻译： 一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流 电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。 可以对包括电荷捕获结构的晶体管计算阈值电压的变化。 参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。