公开(公告)号：US07668010B2

公开(公告)日：2010-02-23

申请号：US12038612

申请日：2008-02-27

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07889556B2

公开(公告)日：2011-02-15

申请号：US12690582

申请日：2010-01-20

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US20100120210A1

公开(公告)日：2010-05-13

申请号：US12690582

申请日：2010-01-20

申请人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07888272B2

公开(公告)日：2011-02-15

申请号：US11609747

申请日：2006-12-12

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

IPC分类号： H01L21/318

CPC分类号： H01L21/3144 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/42332 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/7885

摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

摘要翻译： 半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。 然而，额外的步骤不需要额外的掩模。 因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

公开(公告)号：US20080138998A1

公开(公告)日：2008-06-12

申请号：US11609747

申请日：2006-12-12

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

IPC分类号： H01L21/31

CPC分类号： H01L21/3144 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/42332 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/7885

摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

摘要翻译： 半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。 然而，额外的步骤不需要额外的掩模。 因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。