公开(公告)号：US08593850B2

公开(公告)日：2013-11-26

申请号：US12346706

申请日：2008-12-30

申请人： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

发明人： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC分类号： G11C17/00 ,  G11C17/06 ,  G11C17/18

CPC分类号： G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

公开(公告)号：US08183106B2

公开(公告)日：2012-05-22

申请号：US11460216

申请日：2006-07-26

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

摘要翻译： 一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。 因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。 此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

公开(公告)号：US07889556B2

公开(公告)日：2011-02-15

申请号：US12690582

申请日：2010-01-20

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07666784B2

公开(公告)日：2010-02-23

申请号：US12211603

申请日：2008-09-16

申请人： Miao-Chih Hsu ,  Tzung-Ting Han ,  Ming-Shang Chen

发明人： Miao-Chih Hsu ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11568

摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.

摘要翻译： 使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

公开(公告)号：US20090276737A1

公开(公告)日：2009-11-05

申请号：US12182352

申请日：2008-07-30

申请人： Shaw Hung Ku ,  Chia-Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Chia-Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/78

摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

摘要翻译： 一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流 电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。 可以对包括电荷捕获结构的晶体管计算阈值电压的变化。 参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。

公开(公告)号：US07435648B2

公开(公告)日：2008-10-14

申请号：US11459990

申请日：2006-07-26

申请人： Miao Chih Hsu ,  Tzung Ting Han ,  Ming Shang Chen

发明人： Miao Chih Hsu ,  Tzung Ting Han ,  Ming Shang Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/76838 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11568

摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.

摘要翻译： 使用这种方法形成的接触形成方法和存储器阵列，该方法包括提供存储阵列，该存储阵列具有设置在半导体衬底的表面下方的多个位线，以及设置在衬底的表面上方且横向于衬底的多个字线 位线 在所述多个字线上形成硬掩模材料层，其中在所述硬掩模材料层中的开口下方暴露位于所述位线中的至少一个之上并且在两个连续字线之间的区域; 在硬掩模材料层上形成绝缘材料层; 在所述区域上方的绝缘材料层中形成连续的沟槽和通孔图案，使得所述至少一个位线的一部分暴露在所述图案下方; 以及形成互连，其包括设置在所述连续沟槽中的导电材料和通孔图案，其中所述互连与所述至少一个位线的所述暴露部分导电接触。

公开(公告)号：US07271062B2

公开(公告)日：2007-09-18

申请号：US11223690

申请日：2005-09-09

申请人： Meng-Hsuan Weng ,  Tzung-Ting Han ,  Ming-Shang Chen

发明人： Meng-Hsuan Weng ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在制造方法中，在衬底上形成多个堆叠栅极结构，并且在堆叠栅极结构旁边的衬底中形成多个掺杂区域。 然后，在堆叠栅极结构的侧壁上形成多个间隔物。 之后，在暴露的掺杂区域上形成多个导电焊盘层。 通过形成导电焊盘层，可以减小每个存储单元中的掺杂区域的电阻。

公开(公告)号：US20070057317A1

公开(公告)日：2007-03-15

申请号：US11223690

申请日：2005-09-09

申请人： Meng-Hsuan Weng ,  Tzung-Ting Han ,  Ming-Shang Chen

发明人： Meng-Hsuan Weng ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

公开(公告)号：US20060110879A1

公开(公告)日：2006-05-25

申请号：US10904703

申请日：2004-11-24

申请人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

发明人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在基板上形成多个堆叠栅极条，并且在堆叠栅极条旁边的基板中形成多个源极/漏极区域。 在源/漏区上形成多个介质条。 多个字线形成在堆叠栅极条和介质条上。 此后，除去由字线露出的堆叠栅极条以形成多个开口。 在开口和字线的侧壁上形成多个间隔物。 介电层形成在衬底上。 在电介质层和两个相邻字线之间的介质条形成多个触点。

公开(公告)号：US06960506B2

公开(公告)日：2005-11-01

申请号：US10714128

申请日：2003-11-13

申请人： Hung-Yu Chiu ,  Ming-Shang Chen ,  Wenpin Lu ,  Uway Tseng

发明人： Hung-Yu Chiu ,  Ming-Shang Chen ,  Wenpin Lu ,  Uway Tseng

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of forming a memory device having a self-aligned contact is described. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a first silicon nitride layer on the floating poly gate layer, and forming a patterned photoresist layer on the first silicon nitride layer. The method further includes etching the first silicon nitride layer and the floating poly gate layer using the patterned photoresist layer as an etch mask, forming an oxide layer over the exposed etched areas, removing the patterned photoresist layer and the first silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a second silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

摘要翻译： 描述形成具有自对准接触的存储器件的方法。 该方法包括提供具有形成在其上的浮置栅极介电层的衬底，在浮置栅极电介质层上形成浮动多晶硅栅极层，在浮动多晶硅层上形成第一氮化硅层，并在第一层上形成图案化光致抗蚀剂层 氮化硅层。 该方法还包括使用图案化的光致抗蚀剂层作为蚀刻掩模蚀刻第一氮化硅层和浮动多晶硅层，在暴露的蚀刻区域上形成氧化物层，去除图案化的光致抗蚀剂层和第一氮化硅层， 浮动多晶硅栅极层，在浮动多晶硅层中形成多个空间，以及在浮动多晶硅栅极层的多晶硅间隔上沉积第二个氮化硅层以形成自对准的接触。