公开(公告)号：US07971177B2

公开(公告)日：2011-06-28

申请号：US12182352

申请日：2008-07-30

申请人： Shaw Hung Ku ,  Chia Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Chia Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/78

摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

摘要翻译： 一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流 电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。 可以对包括电荷捕获结构的晶体管计算阈值电压的变化。 参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。

公开(公告)号：US07668010B2

公开(公告)日：2010-02-23

申请号：US12038612

申请日：2008-02-27

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07889556B2

公开(公告)日：2011-02-15

申请号：US12690582

申请日：2010-01-20

申请人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C16/00

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US20090276737A1

公开(公告)日：2009-11-05

申请号：US12182352

申请日：2008-07-30

申请人： Shaw Hung Ku ,  Chia-Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Chia-Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/78

摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

摘要翻译： 一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流 电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。 可以对包括电荷捕获结构的晶体管计算阈值电压的变化。 参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。

公开(公告)号：US20100120210A1

公开(公告)日：2010-05-13

申请号：US12690582

申请日：2010-01-20

申请人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： SHAW-HUNG KU ,  Ten Hao Yeh ,  Shih Chin Lee ,  Shang Wei Lin ,  Chia Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US20090213656A1

公开(公告)日：2009-08-27

申请号：US12038612

申请日：2008-02-27

申请人： Shaw Hung Ku ,  Teng Hao Yeh ,  Shih-Chin Lee ,  Shang-Wei Lin ,  Chia-Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

发明人： Shaw Hung Ku ,  Teng Hao Yeh ,  Shih-Chin Lee ,  Shang-Wei Lin ,  Chia-Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

IPC分类号： G11C11/34 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

公开(公告)号：US07301818B2

公开(公告)日：2007-11-27

申请号：US11224597

申请日：2005-09-12

申请人： Wenpin Lu ,  Shaw Hung Ku

发明人： Wenpin Lu ,  Shaw Hung Ku

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C16/0466

摘要： Hole annealing methods are described after erasure of nitride storage memory cells for compensating trapped holes to minimize the holes from detrapping in order to reduce the amount of threshold voltage from drifting significantly higher. A soft hot electron program is used to selected nitride storage memory cells that have been detected to have a threshold voltage that is higher than a presetting threshold voltage (EV) minus a wordline delta X. The effect of the soft electron program neutralizes the excess holes introduced by erasure of nitride storage memory cells that decreases the amount of threshold voltage from drifting higher. In one embodiment, a hole annealing method describes a soft hot electron programming to nitride storage memory cells in a block of nitride memory array that have been determined to have a threshold voltage higher than the presetting threshold voltage minus the wordline delta X.

公开(公告)号：US06363013B1

公开(公告)日：2002-03-26

申请号：US09652230

申请日：2000-08-29

申请人： Wenpin Lu ,  Ying-Che Lo ,  Ming-Shang Chen ,  Baw-Chyuan Lin ,  Chun-Lien Su

发明人： Wenpin Lu ,  Ying-Che Lo ,  Ming-Shang Chen ,  Baw-Chyuan Lin ,  Chun-Lien Su

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： Method for soft-programming at least one floating gate memory cell in at least one page of a persistent memory device by converging the low threshold voltages of the several cells of the page within an optimal range, and apparatus implementing the method. The methodology of the present invention teaches connecting the individual drains of the several memory cells of the device of a given page, or block, to a voltage limited constant current circuitry component. The methodology applies a first positive voltage to the word line of the page and a second positive voltage to the common source in a fixed time period to converge the pages low threshold voltage distribution. The methodology is capable of implementation on either the source or drain side of the memory array.

摘要翻译： 用于通过将页面的几个单元的低阈值电压收敛在最佳范围内来软编程永久存储器件的至少一页中的至少一个浮动栅极存储单元的方法，以及实现该方法的装置。 本发明的方法教导了将给定页面或块的装置的多个存储器单元的各个漏极连接到电压限制恒流电路部件。 该方法在固定时间段内将第一正电压施加到页的字线和第二正电压到公共源，以使页低收集阈值电压分布。 该方法能够在存储器阵列的源极或漏极侧实现。

公开(公告)号：US20050106819A1

公开(公告)日：2005-05-19

申请号：US10714128

申请日：2003-11-13

申请人： Hung-Yu Chiu ,  Ming-Shang Chen ,  Wenpin Lu ,  Uway Tseng

发明人： Hung-Yu Chiu ,  Ming-Shang Chen ,  Wenpin Lu ,  Uway Tseng

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of forming a memory device having a self-aligned contact is disclosed. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a silicon nitride layer on the floating poly gate layer, and forming a photoresist layer on the silicon nitride layer. The method further includes etching the silicon nitride layer and the floating poly gate layer using the photoresist layer as an etch mask, forming an oxide layer over the exposed areas, removing the photoresist layer and the silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

摘要翻译： 公开了一种形成具有自对准接触的存储器件的方法。 该方法包括提供其上形成有浮置栅极电介质层的衬底，在浮置栅极介电层上形成浮动多晶硅栅极层，在浮动多晶硅层上形成氮化硅层，并在氮化硅层上形成光致抗蚀剂层 。 该方法还包括使用光致抗蚀剂层作为蚀刻掩模蚀刻氮化硅层和浮动多晶硅层，在暴露的区域上形成氧化物层，去除光致抗蚀剂层和氮化硅层以暴露浮动多晶硅栅极层， 在所述浮动多晶硅层中形成多晶硅空间，以及在所述浮动多晶硅栅极层的所述多晶硅间隔上沉积氮化硅层以形成自对准触点。

公开(公告)号：US5912845A

公开(公告)日：1999-06-15

申请号：US926554

申请日：1997-09-10

申请人： Chia-Shing Chen ,  Mam-Tsung Wang ,  Wenpin Lu ,  Ming-Hung Chou ,  Ying-Che Lo ,  Ming-Shang Chen

发明人： Chia-Shing Chen ,  Mam-Tsung Wang ,  Wenpin Lu ,  Ming-Hung Chou ,  Ying-Che Lo ,  Ming-Shang Chen

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/107 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445

摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.

摘要翻译： 一种用于软编程存储单元和浮动栅极存储器件的方法。 在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。 用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。 栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V， 并且阱电压比栅极电压低约4V。