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公开(公告)号：US07733151B1
公开(公告)日：2010-06-08
申请号：US12316166
申请日：2008-12-08
IPC分类号： H03K3/00
CPC分类号： H03K5/1565 , G06F1/08 , H03L7/183
摘要： A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).
摘要翻译： 时钟信号发生器（1）包括需要至少预定的第一频率（fDIGCLK）的参考时钟信号的锁相环（PLL）电路（25）。 将基本上低于第一频率（fDIGCLK）的第二频率（fREF）的第一时钟信号（REFCLK）相乘以便产生具有至少与第一频率一样高的频率的第二时钟信号（DIGCLK） （fDIGCLK），并且其相对于第一时钟信号（REFCLK）是相位锁定的。 第二时钟信号（DIGCLK）被施加到产生输出时钟信号（PLLCLK或CLKOUT）的PLL电路（25）的参考信号输入端。
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公开(公告)号：US07408485B1
公开(公告)日：2008-08-05
申请号：US11726414
申请日：2007-03-22
IPC分类号： H03M7/00
CPC分类号： H03H17/0614 , H03H17/0628
摘要： A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).
摘要翻译： 适用于音频DAC的采样率转换器包括分别产生与异步时钟（MCLK）同步并分别表示周期和边缘到达时间的第一（TR）和第二（STAMPR）信号的第一估计电路（32A） 的参考时钟（REFCLK）。 第二估计电路（32B）对第一和第二信号进行操作以分别产生表示输入采样率（32fsin）和输入数据采样到达时间的第三（T 1）和第四（STAMP 1）信号 到系数和地址发生器（76），以产生输入到以输入采样率接收数字输入数据的FIFO存储器（42）的读地址和系数;以及从FIFO存储器接收数据的乘法/累加电路（78）。 乘法/累积电路以输出采样率（32fsout）产生与异步时钟同步的输出信号（SRC-out）。
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公开(公告)号：US20100141310A1
公开(公告)日：2010-06-10
申请号：US12316166
申请日：2008-12-08
IPC分类号： H03L7/06
CPC分类号： H03K5/1565 , G06F1/08 , H03L7/183
摘要： A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).
摘要翻译： 时钟信号发生器（1）包括需要至少预定的第一频率（fDIGCLK）的参考时钟信号的锁相环（PLL）电路（25）。 将基本上低于第一频率（fDIGCLK）的第二频率（fREF）的第一时钟信号（REFCLK）相乘以便产生具有至少与第一频率一样高的频率的第二时钟信号（DIGCLK） （fDIGCLK），并且其相对于第一时钟信号（REFCLK）是相位锁定的。 第二时钟信号（DIGCLK）被施加到产生输出时钟信号（PLLCLK或CLKOUT）的PLL电路（25）的参考信号输入端。
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