公开(公告)号：US06897102B2

公开(公告)日：2005-05-24

申请号：US10313333

申请日：2002-12-06

申请人： Sheldon Aronowitz ,  Mohammed Mirabedini

发明人： Sheldon Aronowitz ,  Mohammed Mirabedini

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/51 ,  H01L31/113

CPC分类号： H01L21/28194 ,  H01L21/28176 ,  H01L29/513 ,  H01L29/517

摘要： A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate dielectric. Polysilicon is deposited onto the calcium and patterned in a standard way. The exposed calcium is then removed by raising the temperature to approximately 600° C. The calcium remaining between the gate dielectric and the polysilicon blocks channeling of dopant to minimize depletion and penetration, increase conductivity, and allow for longer and higher-temperature annealing.

摘要翻译： 揭示了制备多晶硅栅极以最小化栅极耗尽和掺杂剂穿透并增加电导率的方法。 几个原子的单层会凝结在栅极电介质上。 多晶硅沉积在钙上并以标准方式图案化。 然后通过将温度升高至约600℃来除去暴露的钙。残留在栅极电介质和多晶硅之间的钙阻挡掺杂剂的通道，以使耗尽和穿透最小化，增加导电性，并允许更长时间和更高温退火。