公开(公告)号：US07137095B1

公开(公告)日：2006-11-14

申请号：US10077189

申请日：2002-02-15

申请人： Tong Liu ,  Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Naihui Liao ,  Weidong Xiong

发明人： Tong Liu ,  Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Naihui Liao ,  Weidong Xiong

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.

摘要翻译： 连接所述现场可编程门阵列中的接口组的高速路由系统。 高速公路系统具有第一组路由导体，其被配置为将信号传送到现场可编程门阵列的第一瓦片中的至少一个接口组的输入端口，并且被配置为从现场可编程的其它瓦片的输出端口传送信号 门阵列 第一组导体包括垂直导体，其形成交叉点水平导体和位于垂直导体和水平导体的交叉点处的对准方向的可编程互连元件，以将每个水平导体连接到垂直导体之一。

公开(公告)号：US06700404B1

公开(公告)日：2004-03-02

申请号：US10066398

申请日：2002-01-30

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC分类号： H03K19177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

摘要翻译： 一种装置包括现场可编程门阵列（FPGA）。 所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体 接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。 第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US06611153B1

公开(公告)日：2003-08-26

申请号：US10061955

申请日：2002-01-31

申请人： Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

发明人： Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

IPC分类号： H03K19177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

公开(公告)号：US06870396B2

公开(公告)日：2005-03-22

申请号：US10429004

申请日：2003-04-30

申请人： Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

发明人： Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

摘要翻译： 一种装置包括现场可编程门阵列（FPGA）。 FPGA包括第一FPGA片，并且第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。 常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。 通过根据指示符存放交换机来最大化常规路由结构的可路由性。 这种新颖的指定方法与大约一半的开关提供相同的可路由性。 因此，实现了路由区域的进一步减少。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。

公开(公告)号：US06744278B1

公开(公告)日：2004-06-01

申请号：US10061951

申请日：2002-01-31

申请人： Tong Liu ,  Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Naihui Liao

发明人： Tong Liu ,  Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Naihui Liao

IPC分类号： H03K19177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

公开(公告)号：US06731133B1

公开(公告)日：2004-05-04

申请号：US10077190

申请日：2002-02-15

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

IPC分类号： H03K19177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile. The disclosed apparatus also provides for a routing structure between IGs and RAM blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 一种现场可编程门阵列（FPGA），包括：第一FPGA片，所述第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。 常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。 第一FPGA片还包括独立于常规路由结构的辅路由结构，耦合到每个IG，被配置为将信号从所述第一FPGA片传送到至少另一个FPGA片。 所公开的装置还提供了IG和RAM块之间的路由结构。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交的理由是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US07342416B2

公开(公告)日：2008-03-11

申请号：US11561705

申请日：2006-11-20

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC分类号： H03K19/0177

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

摘要翻译： 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US07157938B2

公开(公告)日：2007-01-02

申请号：US11335396

申请日：2006-01-18

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

摘要翻译： 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US06888375B2

公开(公告)日：2005-05-03

申请号：US10429002

申请日：2003-04-30

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC分类号： H03K19/177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

摘要翻译： 一种装置包括现场可编程门阵列（FPGA）。 所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体 接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。 第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US20080238477A1

公开(公告)日：2008-10-02

申请号：US12036470

申请日：2008-02-25

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC分类号： H03K19/177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

摘要翻译： 一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。 第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。