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公开(公告)号：US08412870B2
公开(公告)日：2013-04-02
申请号：US12878194
申请日：2010-09-09
IPC分类号： G06F13/368
CPC分类号： G06F13/1615
摘要： An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer.
摘要翻译： 一种包括第一子仲裁器电路和第二子仲裁器电路的装置。 第一子仲裁器电路可以被配置为基于第一准则从多个信道请求中确定获胜信道。 第二子仲裁器电路可以被配置为基于第二准则来确定从多个信道请求接收的获胜信道。 第二子仲裁器还可以被配置为如果第二标准创建更有效的数据传输，则通过覆盖第一仲裁器来优化来自第一仲裁器的获胜通道的顺序。
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公开(公告)号：US20110296124A1
公开(公告)日：2011-12-01
申请号：US12899681
申请日：2010-10-07
CPC分类号： G06F12/0284
摘要： An apparatus comprising a plurality of buffers and a channel router circuit. The buffers may be each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The channel router circuit may be configured to connect one or more of the buffers to one of a plurality of memory resources. The channel router circuit may be configured to return a data signal to a respective one of the buffers in an order requested by each of the buffers.
摘要翻译： 一种包括多个缓冲器和通道路由器电路的装置。 缓冲器可以各自被配置为响应于从多个客户端中的相应一个客户端接收到的多个信道请求中的相应一个来产生控制信号。 信道路由器电路可以被配置为将一个或多个缓冲器连接到多个存储器资源之一。 信道路由器电路可以被配置为以每个缓冲器请求的顺序将数据信号返回到相应的一个缓冲器。
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公开(公告)号：US20110276727A1
公开(公告)日：2011-11-10
申请号：US12857716
申请日：2010-08-17
CPC分类号： G06F13/1684 , G06F13/161
摘要： An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.
摘要翻译： 一种包括仲裁器电路，协议引擎电路和信道路由器电路的装置。 仲裁器电路可以被配置为基于第一准则从多个信道请求中确定获胜信道。 多个信道请求中的每一个可以表示具有与存储器的地址边界对准的固定长度的数据突发。 协议引擎电路可以被配置为从仲裁器电路接收指示获胜信道的信号。 协议引擎电路还可以被配置为以等于数据突发的粒度执行存储器协议。 信道路由器电路可以被配置为向仲裁器电路和协议引擎电路呈现多个信道请求。
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公开(公告)号：US20110296068A1
公开(公告)日：2011-12-01
申请号：US12878194
申请日：2010-09-09
IPC分类号： G06F13/368
CPC分类号： G06F13/1615
摘要： An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer.
摘要翻译： 一种包括第一子仲裁器电路和第二子仲裁器电路的装置。 第一子仲裁器电路可以被配置为基于第一准则从多个信道请求中确定获胜信道。 第二子仲裁器电路可以被配置为基于第二准则来确定从多个信道请求接收的获胜信道。 第二子仲裁器还可以被配置为如果第二标准创建更有效的数据传输，则通过覆盖第一仲裁器来优化来自第一仲裁器的获胜通道的顺序。
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公开(公告)号：US08285892B2
公开(公告)日：2012-10-09
申请号：US12857716
申请日：2010-08-17
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G06F13/161
摘要： An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.
摘要翻译： 一种包括仲裁器电路，协议引擎电路和信道路由器电路的装置。 仲裁器电路可以被配置为基于第一准则从多个信道请求中确定获胜信道。 多个信道请求中的每一个可以表示具有与存储器的地址边界对准的固定长度的数据突发。 协议引擎电路可以被配置为从仲裁器电路接收指示获胜信道的信号。 协议引擎电路还可以被配置为以等于数据突发的粒度执行存储器协议。 信道路由器电路可以被配置为向仲裁器电路和协议引擎电路呈现多个信道请求。
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公开(公告)号：US08339891B2
公开(公告)日：2012-12-25
申请号：US12957569
申请日：2010-12-01
IPC分类号： G11C7/00
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit.
摘要翻译： 一种包括多个缓冲器和存储器控制器的装置。 多个缓冲器可以各自被配置为响应于从多个客户端中的相应一个客户端接收到的多个信道请求中的相应一个来生成接入请求信号。 存储器控制器电路可以被配置为响应于多个访问请求信号而生成时钟使能信号。 时钟使能信号可以被配置为启动进入和退出存储器电路的功率节省模式。
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公开(公告)号：US20110296214A1
公开(公告)日：2011-12-01
申请号：US12957569
申请日：2010-12-01
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit.
摘要翻译： 一种包括多个缓冲器和存储器控制器的装置。 多个缓冲器可以各自被配置为响应于从多个客户端中的相应一个客户端接收到的多个信道请求中的相应一个来生成接入请求信号。 存储器控制器电路可以被配置为响应于多个访问请求信号而生成时钟使能信号。 时钟使能信号可以被配置为启动进入和退出存储器电路的功率节省模式。
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