公开(公告)号：US20080046725A1

公开(公告)日：2008-02-21

申请号：US11505347

申请日：2006-08-17

申请人： Shi-Wu Lo ,  Tien-Fu Chen

发明人： Shi-Wu Lo ,  Tien-Fu Chen

IPC分类号： H04L9/00 ,  G06F12/14 ,  H04L9/32 ,  G06F11/30

CPC分类号： G06F9/545 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/53

摘要： A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

摘要翻译： 提供了一种快速系统调用的方法。 首先，使用计算内核服务程序的逻辑操作。 然后将逻辑运算结果与密钥寄存器的密文进行比较。 逻辑运算的至少一个输入来自所需内核服务程序的相关信息。 例如，内核服务程序的起始地址或内核服务程序的起始地址的内容，或其组合。 如果逻辑运算结果等于密钥寄存器的密文，则允许从用户模式切换到内核模式，以读取内核服务程序。 否则，中央处理系统执行相应的异常处理程序。 然后操作系统终止模式切换请求并向操作系统报告错误。

公开(公告)号：US08132002B2

公开(公告)日：2012-03-06

申请号：US11505347

申请日：2006-08-17

申请人： Shi-Wu Lo ,  Tien-Fu Chen

发明人： Shi-Wu Lo ,  Tien-Fu Chen

IPC分类号： G06F21/00

CPC分类号： G06F9/545 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/53

摘要： A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

摘要翻译： 提供了一种快速系统调用的方法。 首先，使用计算内核服务程序的逻辑操作。 然后将逻辑运算结果与密钥寄存器的密文进行比较。 逻辑运算的至少一个输入来自所需内核服务程序的相关信息。 例如，内核服务程序的起始地址或内核服务程序的起始地址的内容，或其组合。 如果逻辑运算结果等于密钥寄存器的密文，则允许从用户模式切换到内核模式，以读取内核服务程序。 否则，中央处理系统执行相应的异常处理程序。 然后操作系统终止模式切换请求并向操作系统报告错误。

公开(公告)号：US07115449B2

公开(公告)日：2006-10-03

申请号：US10867660

申请日：2004-06-16

申请人： Ching-Fa Yeh ,  Tien-Fu Chen ,  Jen-Chung Lou

发明人： Ching-Fa Yeh ,  Tien-Fu Chen ,  Jen-Chung Lou

IPC分类号： H01L21/00

CPC分类号： H01L21/02683 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02686 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757

摘要： The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).

摘要翻译： 本发明提供一种多晶硅薄膜晶体管的制造方法，其通过在单一方向上的各向异性等离子体蚀刻在薄膜晶体管（TFT）的有源层的侧壁上形成硅间隔物。 硅衬垫提供了在侧壁上激光再结晶的机制，以防止活性层在激光再结晶后收缩或脱落。 根据本发明，在生产中可以在通道中形成大的颗粒而不需要额外的掩模。 通过这样做，组件的特性得到提高; 均匀性提高; 生产成本降低。 因此，这种技术将在低温多晶硅薄膜晶体管（LTPS-TFT）领域发挥重要作用。

公开(公告)号：US20060080260A1

公开(公告)日：2006-04-13

申请号：US10963668

申请日：2004-10-13

申请人： Tien-Fu Chen ,  Jui-Lung Shih

发明人： Tien-Fu Chen ,  Jui-Lung Shih

IPC分类号： H04L9/00

CPC分类号： H04L63/0428 ,  H04L9/088 ,  H04L63/06 ,  H04L63/105 ,  H04L2209/603 ,  H04L2463/101

摘要： Disclosed is “System and Method for Digital Content Rights Management on Portable Storage Devices.” Due to the fact that digital content will some become the master industry in the future, a new usage rights management is needed, especially for those storage media such as portable PDA or handy flash. In conventional methods, the network has to be kept alive for determining the license validation. Conversely, the new method only needs to connect to Internet when downloading the digital content that was chosen. The digital content with personal identification and usage rights are encrypted. Henceforth, the digital content is prevented from illegal usage such as copy and unauthorized read. By the usage rights management, several kinds of limitations are defined for being operated in combination with each other, to generate various usage permissions while the overall system is easily managed. This invention is platform independent and suitable for different kinds of portable storage devices.

摘要翻译： 披露的是“便携式存储设备上的数字内容权限管理系统与方法”。 由于数字内容将来会成为主业，因此需要新的使用权管理，特别是对于便携式PDA或便携式闪存等存储媒体。 在常规方法中，网络必须保持活跃以确定许可证验证。 相反，新方法仅在下载所选数字内容时才需要连接到Internet。 具有个人识别和使用权的数字内容被加密。 此后，防止数字内容非法使用，如复制和未经授权的读取。 通过使用权管理，定义了相互操作的几种限制，以便在整个系统易于管理的同时产生各种使用许可。 本发明是平台独立的，适用于不同种类的便携式存储设备。

公开(公告)号：US07667993B2

公开(公告)日：2010-02-23

申请号：US11907524

申请日：2007-10-12

申请人： Chao-Ching Wang ,  Chieh-Jen Cheng ,  Jinn-Shyan Wang ,  Tien-Fu Chen

发明人： Chao-Ching Wang ,  Chieh-Jen Cheng ,  Jinn-Shyan Wang ,  Tien-Fu Chen

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/1075

摘要： A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected to a group of CAM cells. The dual-ported dynamic circuit includes a setting circuit, a first directing circuit, a second directing circuit, a first AND dynamic output circuit and a second AND dynamic output circuit.

摘要翻译： 双端口AND型匹配线电路包括至少一个双端口动态AND门。 双端口动态和门包括一组CAM单元和双端口动态电路。 一组CAM单元连接到双端口动态电路和GND。 双端口动态电路连接到一组CAM单元。 双端口动态电路包括设置电路，第一引导电路，第二引导电路，第一AND动态输出电路和第二AND动态输出电路。

公开(公告)号：US20080022403A1

公开(公告)日：2008-01-24

申请号：US11459349

申请日：2006-07-22

申请人： Tien-Fu Chen ,  Chieh-Jen Cheng

发明人： Tien-Fu Chen ,  Chieh-Jen Cheng

IPC分类号： G06F12/14 ,  G06F11/00 ,  G06F12/16 ,  G06F15/18 ,  G08B23/00

CPC分类号： H04L63/1416

摘要： A multiple skip structure of a pattern matcher uses a shift engine to read a string and divide the string into a front module and a rear module. The shift engine uses the rear module of the string to index the shift index column of a shift table and retrieves a corresponding shift value and signature value back to the shift engine. The shift engine uses the shift value for the first level of filtering. If the shift value indicates a pattern is contained, it then compares a signature value with a shift hash value for a second level of filtering. The shift hash value is obtained from using the front module of the string via a hash function. If the shift hash value equals to the signature value, then it transmits the position of the string to a trie engine for a full pattern matching.

摘要翻译： 模式匹配器的多重跳过结构使用移位引擎读取字符串并将字符串划分成前部模块和后部模块。 换档发动机使用弦的后部模块对换档表的换档指数列进行索引，并将相应的换档值和签名值返回到换档引擎。 换档引擎使用第一级过滤的移位值。 如果移位值指示包含模式，则其将签名值与第二级别的过滤的移位散列值进行比较。 通过散列函数从字符串的前端模块获得移位散列值。 如果移位散列值等于签名值，则将字符串的位置发送到特里引擎以进行完全模式匹配。

公开(公告)号：US20070083576A1

公开(公告)日：2007-04-12

申请号：US11246734

申请日：2005-10-08

申请人： Tien-Fu Chen ,  Chih-Heng Kang ,  Chen-Neng Win

发明人： Tien-Fu Chen ,  Chih-Heng Kang ,  Chen-Neng Win

IPC分类号： G06F15/00

CPC分类号： G06F9/30098 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/383

摘要： An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.

摘要翻译： 提供作为处理单元的组成部分的算术和逻辑器件以实现代码大小和开销降低。 算术和逻辑器件包含几个辅助计算单元，每个辅助计算单元在控制单元的控制下能够进行简单的算术和逻辑运算。 通过沿着数据路径配置辅助计算单元，可以在相同的指令周期内执行操作数的附加处理。 因此，结合这样的算术和逻辑器件的处理单元能够在代码尺寸和存储器访问开销方面实现显着的性能改进。

公开(公告)号：US07109075B2

公开(公告)日：2006-09-19

申请号：US10601701

申请日：2003-06-24

申请人： Ching-Fa Yeh ,  Tien-Fu Chen ,  Jen-Chung Lou

发明人： Ching-Fa Yeh ,  Tien-Fu Chen ,  Jen-Chung Lou

IPC分类号： H01L21/00

CPC分类号： H01L21/02683 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L29/6675 ,  H01L29/78609 ,  H01L29/78672 ,  H01L29/78696

摘要： A method for fabricating polycrystalline silicon film transistors, which includes a polysilicon spacer capping onto a sidewall of an active layer in the thin film transistors by an isotropic dry etching of the silicon film. This method suppresses the shrinkage of the active layer during recrystallization by the laser. Large grains are formed in the channel after recrystallization utilizing a high-energy continuous wavelength laser or an excimer laser annealing the active layer. This process does not require an additional mask. Uniform arrangement of grain boundaries and large grain sizes promotes uniformity of performance of the device, which is important in the fields of low temperature polycrystalline silicon thin film transistors (LTPS-TFTs).

摘要翻译： 一种用于制造多晶硅膜晶体管的方法，其包括通过硅膜的各向同性干蚀刻在薄膜晶体管中的有源层的侧壁上覆盖多晶硅间隔物。 该方法抑制了激光再结晶时有源层的收缩。 在使用高能量连续波长激光器或准分子激光器对活性层进行退火的再结晶后，在通道中形成大的晶粒。 此过程不需要额外的掩码。 晶界均匀排列和晶粒尺寸均匀化，使器件性能均匀化，这在低温多晶硅薄膜晶体管（LTPS-TFT）领域是重要的。

公开(公告)号：US20110307741A1

公开(公告)日：2011-12-15

申请号：US12923913

申请日：2010-10-14

申请人： Tien-Fu Chen ,  Che-Neng Wen ,  Shu-Hsuan Chou ,  Yen-Lan Hsu

发明人： Tien-Fu Chen ,  Che-Neng Wen ,  Shu-Hsuan Chou ,  Yen-Lan Hsu

IPC分类号： G06F11/36

CPC分类号： G06F11/3648 ,  G06F11/3636

摘要： A non-intrusive debugging framework for parallel software based on a super multi-core framework is composed of a plurality of core clusters. Each of the core clusters includes a plurality of core processors and a debug node. Each of the core processors includes a DCP. The DCPs and the debug node are interconnected via at least one channel to constitute a communication network inside each of the core clusters. The core clusters are interconnected via a ring network. In this way, the memory inside each of the debug nodes constitutes a non-uniform debug memory space for debugging without affecting execution of the parallel program, such that it is applicable to current diversified dynamic debugging methods under the super multi-core system.

摘要翻译： 基于超多核框架的并行软件的非侵入性调试框架由多个核心集群组成。 每个核心集群包括多个核心处理器和调试节点。 每个核心处理器都包括一个DCP。 DCP和调试节点经由至少一个信道互连，以构成每个核心集群内的通信网络。 核心集群通过环网互连。 以这种方式，每个调试节点内的内存构成一个不均匀的调试内存空间，用于调试，而不影响并行程序的执行，使其适用于超多核系统下的当前多种动态调试方式。

公开(公告)号：US07987313B2

公开(公告)日：2011-07-26

申请号：US12068752

申请日：2008-02-11

申请人： Shu-Hsuan Chou ,  Ming-Ku Chang ,  Yi-Chao Chan ,  Tien-Fu Chen

发明人： Shu-Hsuan Chou ,  Ming-Ku Chang ,  Yi-Chao Chan ,  Tien-Fu Chen

IPC分类号： G06F13/00 ,  H04L12/28 ,  G08C15/00 ,  H04J1/14

CPC分类号： G06F13/4022 ,  G06F15/17375 ,  G06F15/7825

摘要： A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. Multiple data transfer is provided in parallel between multiple processor cores or multiple functional units and register banks with a dynamic configuration. A low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity, and a simplified circuit is thus obtained.

摘要翻译： 利用片上网络构建分层环结构。 片上网络包括两个0型环形节点和两个1型环形节点。 在多个处理器核心或多个功能单元和具有动态配置的寄存器组之间并行提供多个数据传输。 从而获得了低控制复杂度，优化的局部带宽，优化的远程节点路径，低路由复杂度和简化电路。