公开(公告)号：US5831845A

公开(公告)日：1998-11-03

申请号：US52819

申请日：1998-03-31

申请人： Shi-dong Zhou ,  Derek R. Curd

发明人： Shi-dong Zhou ,  Derek R. Curd

IPC分类号： H02M3/18

CPC分类号： H02M3/073 ,  H02M2003/071

摘要： A voltage regulator for a charge pump is provided with two input paths from a reference input voltage to a comparator, each path having a node between a capacitor pair. The two paths are alternately initialized and used to control the charge pump which generates a reference output voltage, so that the reference output voltage tracks the reference input voltage at all times. Each path has its own capacitor divider and switching circuitry to alternately connect the nodes between the respective pairs of capacitors to the comparator, which compares the nodes to a second voltage reference. Since the circuit is alternately initialized, any alterations to the voltage introduced at the nodes between each of the two capacitor pairs, are corrected to the proper level within a short time.

摘要翻译： 用于电荷泵的电压调节器具有从参考输入电压到比较器的两个输入路径，每个路径具有电容器对之间的节点。 这两个路径被交替地初始化并用于控制产生参考输出电压的电荷泵，使得参考输出电压始终跟踪参考输入电压。 每个路径都有自己的电容分压器和开关电路，用于交替地将各对电容器之间的节点连接到比较器，比较器将节点与第二个参考电压进行比较。 由于电路被交替初始化，所以在两个电容器对中的每一个之间的节点处引入的电压的任何改变在短时间内被校正到适当的电平。

公开(公告)号：US06307420B1

公开(公告)日：2001-10-23

申请号：US09611495

申请日：2000-07-07

申请人： Shi-dong Zhou

发明人： Shi-dong Zhou

IPC分类号： A03K1716

CPC分类号： H03K17/6872 ,  H03K17/164

摘要： A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its voltage loss.

摘要翻译： 斜坡电路逐渐对存储单元施加擦除电压。 在斜坡电路内，公开了NMOS晶体管，其响应于外部斜坡电压逐渐将擦除电压提供给存储器单元。 NMOS晶体管提供擦除电压，直到晶体管的损耗电压限制了NMOS晶体管可以提供的最大擦除电压。 该说明书然后公开了一种PMOS晶体管，当NMOS晶体管不再能够这样做时，该晶体管工作以将擦除电压提供给存储单元。 PMOS晶体管连接到控制电路，其保持PMOS晶体管不活动，直到NMOS晶体管的输出电压受其电压损耗的限制。

公开(公告)号：US5831460A

公开(公告)日：1998-11-03

申请号：US806998

申请日：1997-02-26

申请人： Shi-dong Zhou

发明人： Shi-dong Zhou

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power-on reset (POR) circuit including a first single-level POR, a second single-level POR, a combining circuit, and a latch. Responsive to the voltage on a voltage supply terminal, the first single-level POR generates a first reset signal which terminates at a first trigger level voltage, and the second single-level POR generates a second reset signal which terminates at a second trigger level voltage. A combining circuit logically combines the first and second reset signals, and generates a combined output signal. This output signal controls a latch which provides the POR signal. When the supply voltage is below both trigger levels a POR signal is generated. When the supply voltage is above both trigger levels, no POR signal is generated. When the supply voltage is between trigger levels of the two POR circuits, the combining circuit leaves a floating output signal. Thus the latch does not switch. Thus, the output of the POR circuit provides a reset pulse which, at power-up is triggered at the first (higher) single-level POR trigger level voltage, and during brown-out is triggered by the second (lower) single-level POR trigger level voltage.

摘要翻译： 包括第一单级POR，第二单级POR，组合电路和锁存器的上电复位（POR）电路。 响应于电压供应端子上的电压，第一单电平POR产生终止于第一触发电平电压的第一复位信号，并且第二单电平POR产生第二复位信号，其以第二触发电平电压 。 组合电路逻辑地组合第一和第二复位信号，并且产生组合的输出信号。 该输出信号控制提供POR信号的锁存器。 当电源电压低于两个触发电平时，产生POR信号。 当电源电压高于两个触发电平时，不产生POR信号。 当电源电压在两个POR电路的触发电平之间时，组合电路留下浮动输出信号。 因此闩锁不切换。 因此，POR电路的输出提供复位脉冲，其在上电在第一（较高）单级POR触发电平电压下触发，并且在欠压期间由第二（较低）单级触发 POR触发电平电压。

公开(公告)号：US5828236A

公开(公告)日：1998-10-27

申请号：US801408

申请日：1997-02-20

申请人： Shi-dong Zhou

发明人： Shi-dong Zhou

IPC分类号： H03K19/0185 ,  H03K19/20 ,  H03K19/0948

CPC分类号： H03K19/018585

摘要： A selectable inverter circuit. An inverter circuit receives an input signal which is complemented before becoming an output signal. A pass-through circuit for setting the output signal equivalent to the input signal. An enabling circuit for providing power to the inverter circuit, in response to a selection signal. The enabling circuit also provides a charge storing circuit with a supplemental charge. The charge storing circuit releasing the supplemental charge to the inverter circuit, and so provides the inverter circuit with even more power. The enabling circuit activating the pass-through circuit and deactivating the inverter circuit in response to the first state of the selection signal. The enabling circuit deactivating the pass-through circuit and activating the inverter circuit in response to the second state of the selection signal.

摘要翻译： 可选择的逆变电路。 逆变器电路在成为输出信号之前接收补充的输入信号。 用于设置与输入信号相当的输出信号的通过电路。 一种用于响应于选择信号向逆变器电路提供电力的使能电路。 使能电路还提供具有补充电荷的电荷存储电路。 电荷存储电路将补充电荷释放到逆变器电路，从而为逆变器电路提供更多的功率。 所述使能电路响应于所述选择信号的第一状态激活所述通过电路并使所述逆变器电路停用。 使能电路响应于选择信号的第二状态，去激活直通电路并激活逆变器电路。

公开(公告)号：US06985019B1

公开(公告)日：2006-01-10

申请号：US10823450

申请日：2004-04-13

申请人： Shi-dong Zhou ,  Ping Zhang ,  Ronald L. Cline

发明人： Shi-dong Zhou ,  Ping Zhang ,  Ronald L. Cline

IPC分类号： H03K5/08

CPC分类号： H03K19/018507

摘要： A selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the signal discharge transistor. For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit.

摘要翻译： 用于限制相关联的集成电路（IC）器件的输入/输出（I / O）引脚上的电压过冲的有选择地使能的钳位电路包括单个放电晶体管和选择电路。 单个放电晶体管连接在I / O引脚和地电位之间，选择电路耦合到I / O引脚，并包括一个输入端，用于接收使能信号和耦合到信号放大晶体管的栅极的输出。 对于一些实施例，选择电路包括电平移位器电路和电压检测电路。

公开(公告)号：US06842043B1

公开(公告)日：2005-01-11

申请号：US10386993

申请日：2003-03-11

申请人： Andy T. Nguyen ,  Shi-dong Zhou ,  Ronald L. Cline

发明人： Andy T. Nguyen ,  Shi-dong Zhou ,  Ronald L. Cline

IPC分类号： H03K3/356 ,  H03K19/0175

CPC分类号： H03K3/356113

摘要： Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.

摘要翻译： 电平移位器电路在产生小撬棒电流时改变状态时提供快速操作。 提出了各种实施例，其包括添加到传统电平移位器中的一些以下特征：耦合到每个输出节点并由相关联的输入信号选通的附加下拉晶体管; 耦合到每个输出节点或交叉耦合内部节点并由相关联的输入信号选通的附加上拉晶体管; 耦合到交叉耦合内部节点并由相对输出节点选通的附加上拉晶体管; 并且输出节点上的附加下拉晶体管由低电压功率高。 这些附加晶体管中的一些允许输入信号在输出节点上更快地操作，从而导致输出信号上的更快速的转换并减少撬棒电流。 通过低电压电源门控的下拉电阻确保在上电序列期间发生短路或无短路电流。

公开(公告)号：US06683481B1

公开(公告)日：2004-01-27

申请号：US10162236

申请日：2002-06-03

申请人： Shi-dong Zhou ,  Andy T. Nguyen

发明人： Shi-dong Zhou ,  Andy T. Nguyen

IPC分类号： H03L700

CPC分类号： H03K17/223

摘要： A power on reset (POR) generator circuit includes a modified bandgap POR circuit in series with a modified RC POR circuit. During a fast or slow power up, the circuit behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage. During a fast power up, the capacitor on the bandgap output signal ensures that the POR signal remains active long enough to reset the associated circuitry. During a slow power up, the capacitor prevents glitches in the bandgap output from being passed to the POR output signal. A feedback pulldown optionally included in the bandgap portion of the circuit helps to prevent glitches from reaching the POR output signal by raising the voltage on the internal node after the reference voltage is exceeded. Various embodiments include programmable logic devices and systems that include the described circuits.

摘要翻译： 上电复位（POR）发生器电路包括与改进的RC POR电路串联的改进的带隙POR电路。 在快速或慢速上电期间，电路的行为像传统的带隙POR电路，当内部节点上的电压升高到高于参考电压时，提供POR信号。 在快速上电期间，带隙输出信号上的电容器可确保POR信号保持足够长的时间以复位相关的电路。 在缓慢上电期间，电容器可防止带隙输出中的毛刺传递到POR输出信号。 可选地包括在电路的带隙部分中的反馈下拉有助于通过在超过参考电压之后通过提高内部节点上的电压来防止毛刺到达POR输出信号。 各种实施例包括包括所述电路的可编程逻辑器件和系统。

公开(公告)号：US06456126B1

公开(公告)日：2002-09-24

申请号：US09865871

申请日：2001-05-25

申请人： Jack Siu Cheung Lo ,  Shankar Lakkapragada ,  Shi-dong Zhou

发明人： Jack Siu Cheung Lo ,  Shankar Lakkapragada ,  Shi-dong Zhou

IPC分类号： H03B1900

CPC分类号： H03K5/00006 ,  H03K5/151

摘要： An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

摘要翻译： 描述集成的时钟倍增器和极性控制电路。 该电路在输入信号和输出信号之间提供高速响应，通过使输入信号通过延迟电路实现时钟倍增，并使用延迟电路的输出在两条路径之间选择反相或不反相输入信号以产生 输出信号。 在一个实施例中，反相路径是具有输入端子接收输入信号的CMOS反相器，提供输出信号的输出端子和由延迟电路控制的功率端子。

公开(公告)号：US07236004B1

公开(公告)日：2007-06-26

申请号：US11238780

申请日：2005-09-29

申请人： Shi-dong Zhou ,  Gubo Huang

发明人： Shi-dong Zhou ,  Gubo Huang

IPC分类号： H03K19/003

CPC分类号： H04L25/0272

摘要： Apparatus and method for providing reference voltages for differential signaling with tracking of output differential voltage relative to output offset voltage are described. A swing reference voltage, an offset reference voltage, a swing feedback voltage, and an offset feedback voltage are obtained. Differences between pairs of these voltages are differentially amplified to produce first and second bias voltages. Pull-up and pull-down voltages are driven partially responsive to the first bias voltage and the second bias voltage to provide first and second control voltages. The first control voltage may be provided to a first resistance for the driving of the first pull-up and pull-down voltages. The second control voltage may be provided to a second resistance for the driving of the second pull-up and pull-down voltages. The first control voltage and the second control voltage may be provided to a third resistance.

摘要翻译： 描述了用于为差分信号提供参考电压的设备和方法，其具有相对于输出偏移电压的输出差分电压的跟踪。 获得摆幅参考电压，偏移参考电压，摆动反馈电压和偏移反馈电压。 这些电压对之间的差异被差分放大以产生第一和第二偏置电压。 部分地响应于第一偏置电压和第二偏置电压驱动上拉和下拉电压以提供第一和第二控制电压。 可以将第一控制电压提供给用于驱动第一上拉和下拉电压的第一电阻。 可以将第二控制电压提供给用于驱动第二上拉和下拉电压的第二电阻。 第一控制电压和第二控制电压可以被提供给第三电阻。

公开(公告)号：US07071732B1

公开(公告)日：2006-07-04

申请号：US10732334

申请日：2003-12-09

申请人： Tetse Jang ,  Shi-dong Zhou

发明人： Tetse Jang ,  Shi-dong Zhou

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centralized interconnect structure. The interconnect structure includes numbers of interconnect lines segmented into shorter lengths. Programmable multiplexer circuits couple the segmented interconnect lines to the function blocks and I/O blocks. Programmable switch matrices couple the segmented interconnect lines together into longer interconnect lines of the desired length.

摘要翻译： 复杂的可编程逻辑器件（CPLD）可以在尺寸上向上扩展，而不会增加管芯尺寸或信号延迟。 CPLD包括二维阵列，其包括功能块的行和列以及通过非集中式互连结构可编程地互连的输入/输出（I / O）块。 互连结构包括分割成较短长度的互连线数。 可编程多路复用器电路将分段互连线耦合到功能块和I / O块。 可编程开关矩阵将分段互连线连接在一起成为所需长度的更长的互连线。