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    High-speed, low current level shifter circuits for integrated circuits having multiple power supplies
    1.
    发明授权
    High-speed, low current level shifter circuits for integrated circuits having multiple power supplies 有权
    具有多个电源的集成电路的高速，低电流电平移位器电路

    公开(公告)号：US06842043B1

    公开(公告)日：2005-01-11

    申请号：US10386993

    申请日：2003-03-11

    申请人： Andy T. Nguyen ,  Shi-dong Zhou ,  Ronald L. Cline

    发明人： Andy T. Nguyen ,  Shi-dong Zhou ,  Ronald L. Cline

    IPC分类号： H03K3/356 ,  H03K19/0175

    CPC分类号： H03K3/356113

    摘要： Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.

    摘要翻译： 电平移位器电路在产生小撬棒电流时改变状态时提供快速操作。 提出了各种实施例，其包括添加到传统电平移位器中的一些以下特征：耦合到每个输出节点并由相关联的输入信号选通的附加下拉晶体管; 耦合到每个输出节点或交叉耦合内部节点并由相关联的输入信号选通的附加上拉晶体管; 耦合到交叉耦合内部节点并由相对输出节点选通的附加上拉晶体管; 并且输出节点上的附加下拉晶体管由低电压功率高。 这些附加晶体管中的一些允许输入信号在输出节点上更快地操作，从而导致输出信号上的更快速的转换并减少撬棒电流。 通过低电压电源门控的下拉电阻确保在上电序列期间发生短路或无短路电流。

    Power on reset generator circuit providing hysteresis in a noisy power environment
    2.
    发明授权
    Power on reset generator circuit providing hysteresis in a noisy power environment 有权
    电源复位发电机电路在噪声电源环境中提供滞后

    公开(公告)号：US06683481B1

    公开(公告)日：2004-01-27

    申请号：US10162236

    申请日：2002-06-03

    申请人： Shi-dong Zhou ,  Andy T. Nguyen

    发明人： Shi-dong Zhou ,  Andy T. Nguyen

    IPC分类号： H03L700

    CPC分类号： H03K17/223

    摘要： A power on reset (POR) generator circuit includes a modified bandgap POR circuit in series with a modified RC POR circuit. During a fast or slow power up, the circuit behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage. During a fast power up, the capacitor on the bandgap output signal ensures that the POR signal remains active long enough to reset the associated circuitry. During a slow power up, the capacitor prevents glitches in the bandgap output from being passed to the POR output signal. A feedback pulldown optionally included in the bandgap portion of the circuit helps to prevent glitches from reaching the POR output signal by raising the voltage on the internal node after the reference voltage is exceeded. Various embodiments include programmable logic devices and systems that include the described circuits.

    摘要翻译： 上电复位（POR）发生器电路包括与改进的RC POR电路串联的改进的带隙POR电路。 在快速或慢速上电期间，电路的行为像传统的带隙POR电路，当内部节点上的电压升高到高于参考电压时，提供POR信号。 在快速上电期间，带隙输出信号上的电容器可确保POR信号保持足够长的时间以复位相关的电路。 在缓慢上电期间，电容器可防止带隙输出中的毛刺传递到POR输出信号。 可选地包括在电路的带隙部分中的反馈下拉有助于通过在超过参考电压之后通过提高内部节点上的电压来防止毛刺到达POR输出信号。 各种实施例包括包括所述电路的可编程逻辑器件和系统。

    Self-regulating high voltage ramp up circuit
    3.
    发明授权
    Self-regulating high voltage ramp up circuit 有权
    自调节高压斜升电路

    公开(公告)号：US06628151B1

    公开(公告)日：2003-09-30

    申请号：US10136115

    申请日：2002-04-30

    申请人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen

    发明人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen

    IPC分类号： H03K406

    CPC分类号： H03K17/223 ,  H03K4/50

    摘要： A self-regulating ramp up circuit generates a high voltage signal having a slow, smooth ramp up and reduced process and temperature variation. The circuit uses a resistor and a capacitor to control the rate at which the output signal changes state. In one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level and having a resistor in the pulldown path. The circuit output node is coupled to the output node of the inverter through a capacitor, and to the high voltage power supply through a pullup gated by the output node of the inverter. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the capacitor and/or resistor have programmable capacitance/resistance values.

    摘要翻译： 自调节斜坡电路产生具有缓慢，平滑的上升和降低的工艺和温度变化的高电压信号。 电路使用电阻和电容来控制输出信号变化的速率。 在一个实施例中，使用电平移位器将在低电压电平下工作的使能信号转换到期望的高电压电平。 使用在高电压电平下工作并在下拉路径中具有电阻器的逆变器来反转所得到的值。 电路输出节点通过电容器耦合到逆变器的输出节点，并通过由逆变器的输出节点选通的上拉电路连接到高压电源。 在一些实施例中，斜坡上升电路形成可编程逻辑器件（PLD）的一部分，并且电容器和/或电阻器具有可编程的电容/电阻值。

    Large loading split I/O driver with negligible crowbar
    4.
    发明授权
    Large loading split I/O driver with negligible crowbar 有权
    大容量分流I / O驱动器，可以忽略不计

    公开(公告)号：US07317333B1

    公开(公告)日：2008-01-08

    申请号：US11055228

    申请日：2005-02-10

    申请人： Shi-dong Zhou ,  Andy T. Nguyen

    发明人： Shi-dong Zhou ,  Andy T. Nguyen

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/0013 ,  H03K19/018528

    摘要： A pre-driver for large I/O pull-up and pull-down transistors is provided so that the I/O pull-up and pull-down transistors do not experience crowbar current, and the pre-driver circuit likewise does not experience crowbar current or require large driver transistors. One pre-driver circuit includes two NAND gates and two NOR gates with delay circuitry provided by two series inverters from a data input to a first node, and two additional series inverters from the first node to a second node. A further pre-driver circuit includes feedback from the pre-driver outputs to ensure its NMOS and PMOS transistors do not turn on together to create crowbar, while allowing faster switching. With the pre-driver circuit embodiments, a conventional level shifter can be used. Further with the pre-driver circuitry, slew rate control can be provided in the pull-up and pull-down driver circuitry, rather than in the pre-driver circuitry.

    摘要翻译： 提供了用于大型I / O上拉和下拉晶体管的预驱动器，使得I / O上拉和下拉晶体管不会遇到撬棒电流，并且预驱动器电路同样不会遇到撬棒 电流或需要大的驱动晶体管。 一个预驱动器电路包括两个NAND门和两个NOR门，其中具有从数据输入到第一节点的两个串联反相器提供的延迟电路，以及从第一节点到第二节点的两个附加的串联反相器。 进一步的预驱动电路包括来自预驱动器输出的反馈，以确保其NMOS和PMOS晶体管不会一起导通，以创建撬棒，同时允许更快的切换。 利用预驱动器电路实施例，可以使用传统的电平转换器。 此外，通过预驱动器电路，可以在上拉和下拉驱动器电路中提供压摆率控制，而不是在预驱动器电路中。

    Glitchless clock selection circuit using phase detection switching
    5.
    发明授权
    Glitchless clock selection circuit using phase detection switching 有权
    无差频时钟选择电路采用相位检测切换

    公开(公告)号：US07071738B1

    公开(公告)日：2006-07-04

    申请号：US10877620

    申请日：2004-06-24

    申请人： Andy T. Nguyen ,  Shi-dong Zhou

    发明人： Andy T. Nguyen ,  Shi-dong Zhou

    IPC分类号： G06F1/08

    CPC分类号： G06F1/08

    摘要： A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.

    摘要翻译： 时钟选择电路包括输出多路复用器，控制逻辑和边缘检测逻辑。 多路复用器包括用于接收多个输入时钟信号的输入端，用于产生输出时钟信号的输出端和用于接收同步时钟选择信号的控制端子。 控制逻辑包括用于接收时钟选择信号的第一输入端，用于接收第一控制时钟信号的第二输入端，接收同步信号的第三输入端和用于选择性地更新具有时钟转换的同步时钟选择信号的输出端 选择信号。 边缘检测逻辑包括用于接收多个输入时钟信号的第一输入端，用于接收第二控制时钟信号的第二输入端和产生同步信号的输出端。

    Delay lock loop using shift register with token bit to select adjacent clock signals
    6.
    发明授权
    Delay lock loop using shift register with token bit to select adjacent clock signals 有权
    延迟锁定环使用带有令牌位的移位寄存器来选择相邻的时钟信号

    公开(公告)号：US06847241B1

    公开(公告)日：2005-01-25

    申请号：US10627457

    申请日：2003-07-25

    申请人： Andy T. Nguyen ,  Shi-dong Zhou

    发明人： Andy T. Nguyen ,  Shi-dong Zhou

    IPC分类号： H03L7/081 ,  H03L7/06

    CPC分类号： H03L7/0814

    摘要： Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.

    摘要翻译： 提供无毛刺输出时钟信号的延迟锁定环（DLL）电路，系统和方法。 通过使用包括单个令牌位的移位寄存器来选择许多延迟时钟信号之一，从输出时钟信号中消除毛刺。 DLL时钟多路复用器包括一系列移位寄存器，每个移位寄存器在每个阶段只选择许多输入时钟信号中的一个。 因此，在任何给定时间仅选择一个时钟信号。 通过移位每个移位寄存器中的令牌位来增加或减少延迟。 令牌位一次移位一个位置。 因此，不会发生毛刺。

    Programmable differential signaling system
    7.
    发明授权
    Programmable differential signaling system 有权
    可编程差分信号系统

    公开(公告)号：US07479805B1

    公开(公告)日：2009-01-20

    申请号：US11888790

    申请日：2007-08-01

    申请人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen ,  Ronald L. Cline

    发明人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen ,  Ronald L. Cline

    IPC分类号： H03K19/0175

    CPC分类号： H04L25/028 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/0288

    摘要： A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

    摘要翻译： 可编程差分信号系统包括可编程偏置发生器和多个输入/输出模块。 可编程偏置发生器被可操作地耦合以基于多个差分信号约定中的一个的期望信号特性产生第一全局偏置信号和第二全局信号。 多个输入/输出模块可操作地耦合以在差分信令和单端信令之间进行转换，其中基于第一和第二全局偏置信号来调节差分信令的实际信号特性以基本上等于期望的信号特性。

    Programmable differential signaling system
    9.
    发明授权
    Programmable differential signaling system 有权
    可编程差分信号系统

    公开(公告)号：US07265586B1

    公开(公告)日：2007-09-04

    申请号：US11067422

    申请日：2005-02-25

    申请人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen ,  Ronald L. Cline

    发明人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen ,  Ronald L. Cline

    IPC分类号： H03K19/0175

    CPC分类号： H04L25/028 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/0288

    摘要： A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

    摘要翻译： 可编程差分信号系统包括可编程偏置发生器和多个输入/输出模块。 可编程偏置发生器被可操作地耦合以基于多个差分信号约定中的一个的期望信号特性产生第一全局偏置信号和第二全局信号。 多个输入/输出模块可操作地耦合以在差分信令和单端信令之间进行转换，其中基于第一和第二全局偏置信号来调节差分信令的实际信号特性以基本上等于期望的信号特性。