公开(公告)号：US06179619B2

公开(公告)日：2001-01-30

申请号：US09214786

申请日：1999-01-12

申请人： Shigenobu Tanaka

发明人： Shigenobu Tanaka

IPC分类号： G09B905

CPC分类号： A63G7/00 ,  A63G31/16

摘要： A game machine for a moving object having both a position detecting device being operable to detect a position of a person riding on the moving object on a course of movement to obtain position information and a direction detection device being operable to detect a direction of a field of vision of the person to obtain direction information. The game machine also has a memory being operable to store visual and auditory information regarding a change in the course of movement and a central processing part being operable to select visual and auditory information corresponding to the position of the person and the direction of the field of vision of the person riding on the moving object based on the position information of the position detection device and the direction information of the direction detection device. A speaker and a display are used to output the selected auditory and visual information, respectively.

摘要翻译： 一种用于移动物体的游戏机，具有位置检测装置，其可操作以检测在运动过程中骑在所述移动物体上的人的位置，以获得位置信息，并且方向检测装置可操作以检测场的方向 的人的视野来获取方向信息。 游戏机还具有可操作的存储器，用于存储关于移动过程中的变化的视觉和听觉信息，以及中央处理部分，其可操作以选择与人的位置和场的方向相对应的视觉和听觉信息 基于位置检测装置的位置信息和方向检测装置的方向信息，骑在运动物体上的人的视觉。 扬声器和显示器分别用于输出所选择的听觉和视觉信息。

公开(公告)号：US5109395A

公开(公告)日：1992-04-28

申请号：US641153

申请日：1991-01-14

申请人： Shigenobu Tanaka

发明人： Shigenobu Tanaka

IPC分类号： H03M3/04 ,  G06F7/68 ,  H03H17/00 ,  H03H17/06

CPC分类号： H03H17/0664 ,  G06F7/68 ,  H03H2218/10

摘要： A decimetor circuit is constructed to execute an FIR filtering of "n" taps for input data sampled with a sampling frequency "f" and then to resample an output of the FIR filter at a frequency of "f/m". A first counter of a "divided-by-n/m" type is driven with a clock having a frequency of "n/m" of the sampling frequency "f" and selectively operates either in a first counting condition in which the first counter is incremented by one count with each clock pulse of the clock or in a second counting condition in which the first counter is incremented by two counts with each clock pulse of the clock. A second counter of a "divided-by-n" type is driven with the clock and incremented by one count with each clock pulse of the clock. A first decoder is coupled to the second counter for decoding a content of the second counter so as to bring the first counter either into the first counting condition or into the second counting condition. An address generation circuit is connected to the first and second counters for generating an address obtained by adding a "m/n" of the content of the second counter with "m" times of a content of the first counter. A coefficient memory receives the address for outputting a coefficient designated by the received address, and a multiplier multiplies the input data by the received coefficient. An adder circuit has a first input connected to receive the result of multiplication, and a second input connected to a "n/m"-stage shift register which receives an output of the adder circuit and is shifted by the clock so as to output a shifted data from a final stage of the "n/m"-stage shift register. A latch circuit periodically latch the output of the adder circuit.

摘要翻译： 构造分解电路，对采样频率为“f”的输入数据执行“n”抽头的FIR滤波，然后以“f / m”的频率对FIR滤波器的输出进行重新取样。 “n / m”分频的第一计数器由具有采样频率“f”的频率“n / m”的时钟驱动，并且选择性地在第一计数条件下操作，其中第一计数器 用时钟的每个时钟脉冲递增一个计数，或者在第二计数条件中增加一个计数，其中第一计数器与时钟的每个时钟脉冲相加两个计数。 “分频”类型的第二个计数器由时钟驱动，并以时钟的每个时钟脉冲递增一个计数。 第一解码器耦合到第二计数器，用于对第二计数器的内容进行解码，以使第一计数器进入第一计数条件或第二计数条件。 地址产生电路连接到第一和第二计数器，用于产生通过将第二计数器的内容的“m / n”与第一计数器的内容的“m”次相加而获得的地址。 系数存储器接收用于输出由接收地址指定的系数的地址，乘法器将输入数据乘以接收系数。 加法器电路具有连接以接收乘法结果的第一输入端和连接到“n / m”级移位寄存器的第二输入端，其接收加法器电路的输出并被时钟偏移，以输出 从“n / m”级移位寄存器的最后一级移位数据。 锁存电路周期性地锁存加法器电路的输出。

公开(公告)号：US4881169A

公开(公告)日：1989-11-14

申请号：US118015

申请日：1987-11-09

申请人： Shigenobu Tanaka ,  Tomohisa Arai

发明人： Shigenobu Tanaka ,  Tomohisa Arai

IPC分类号： G06F3/06 ,  G06F11/34 ,  G11B20/18

CPC分类号： G11B20/18 ,  G06F11/34 ,  G11B2020/10916

摘要： An apparatus for controlling peripheral equipment includes a circuit for driving the peripheral equipment, first and second registers for storing conditions under which the peripheral equipment is operated, and a timer for counting a time of operation of the peripheral equipment based on data stored in the second register. The content of the first register is written into the second when all zeros are stored in the latter. When the counted time becomes equal to a predetermined time, a time over signal, indicating that an operation time of a specific piece of peripheral equipment is longer than a normal operation time, is produced so that it is possible for a single common timer to count the operation time of a plurality of peripheral equipment.

摘要翻译： 一种用于控制外围设备的设备包括用于驱动外围设备的电路，用于存储周边设备运行的条件的第一和第二寄存器，以及用于根据存储在第二个设备中的数据对周边设备的操作时间进行计数的定时器 寄存器。 当全部零存储在后者中时，第一个寄存器的内容被写入第二个寄存器。 当计数时间等于预定时间时，产生指示特定外围设备的操作时间比正常操作时间长的时间信号，使得单个公共定时器可以计数 多个周边设备的操作时间。

公开(公告)号：US4002011A

公开(公告)日：1977-01-11

申请号：US636202

申请日：1975-11-28

申请人： Shigenobu Tanaka ,  Seiichi Nishikawa ,  Seiji Ishikawa

发明人： Shigenobu Tanaka ,  Seiichi Nishikawa ,  Seiji Ishikawa

IPC分类号： D02G3/36 ,  H01B13/26 ,  D07B3/04

CPC分类号： H01B13/26 ,  D07B7/14

摘要： Disclosed is a high speed binding device wherein a package wound with a binding thread is fixed to a flange of a flyer with its thread-winding axis in parallel with the rotation axis of said flyer and the binding thread is drawn out in the direction of the winding axis; and thereafter said binding thread is passed through a first tensioner for imparting to the binding thread a back tension decreased with a rise in the rotation speed of the flyer and then through a second tensioner for imparting to the binding thread a back tension increased with a rise in said rotation speed, thereby to cause said decrease in the back tension to be offset by said increase in the back tension, thus to bind, with a substantially constant back tension, the binding thread about the outer periphery of an element assembly passing through a through hole coaxially bored through the flyer.

摘要翻译： 公开了一种高速装订装置，其中缠绕有装订螺纹的包装被固定到传单的凸缘上，其缠绕轴线与所述传单的旋转轴线平行，并且装订线沿着 绕轴; 然后，所述装订线通过第一张紧器，用于赋予所述装订线，随着所述传单的旋转速度的上升，所述后张力随着所述传单的旋转速度的上升而减小，然后通过第二张紧器，用于赋予所述装订螺纹， 在所述转速中，从而使所述背张力的所述减小由于所述背张力的增加而被抵消，从而以大致恒定的背张力将所述装订螺纹围绕通过一个元件组件的所述元件组件的外周缘 通孔同轴地穿过传单。

公开(公告)号：US06411558B1

公开(公告)日：2002-06-25

申请号：US09466399

申请日：1999-12-17

申请人： Shigenobu Tanaka

发明人： Shigenobu Tanaka

IPC分类号： G11C700

CPC分类号： H03K17/162 ,  H03K17/693

摘要： The semiconductor device of the present invention includes a failure diagnostic device for diagnosing a memory to detect a failed address; and a failed bit compensation device for compensating a failed bit in the memory which is specified by the failed address, based on the diagnostic result by the failure diagnostic device. The failure diagnostic device diagnoses the memory within the address area for specified data to be stored in the memory. The failure diagnostic device diagnoses the memory outside the address area for storing the data, and detects a normal address, and the failed bit compensation device substitutes the failed address for the normal address.

摘要翻译： 本发明的半导体器件包括用于诊断存储器以检测失败地址的故障诊断装置; 以及基于故障诊断装置的诊断结果的用于补偿由故障地址指定的存储器中的故障位的故障比特补偿装置。 故障诊断装置诊断存储在存储器中的指定数据的地址区域内的存储器。 故障诊断装置诊断用于存储数据的地址区域之外的存储器，并检测正常地址，并且故障位补偿装置将失败的地址替换为正常地址。

公开(公告)号：US5905033A

公开(公告)日：1999-05-18

申请号：US41644

申请日：1998-03-13

申请人： Mikio Morita ,  Shigenobu Tanaka ,  Yuji Yokota ,  Isao Yumoto ,  Tetsuro Kusakabe

发明人： Mikio Morita ,  Shigenobu Tanaka ,  Yuji Yokota ,  Isao Yumoto ,  Tetsuro Kusakabe

IPC分类号： C12N1/00 ,  C12N1/20 ,  C12P7/56 ,  C12R1/225 ,  C12N1/12

CPC分类号： C12R1/225 ,  C12N1/20 ,  C12P7/56

摘要： A method of preparing a culture medium, including the steps of milling entrails of an aquatic product selected from fishes, shells and cephalopods; diluting the milled product with water; and hydrolyzing the diluted product. The culture medium is used for proliferating microorganisms.

摘要翻译： 一种制备培养基的方法，包括研磨鱼，贝壳和头足类动物的水产品的内脏的步骤; 用水稀释碾磨的产品; 并水解稀释的产物。 培养基用于增殖微生物。

公开(公告)号：US4013948A

公开(公告)日：1977-03-22

申请号：US604028

申请日：1975-08-12

申请人： Shigenobu Tanaka ,  Hikaru Yasuhara ,  Munesuke Oguchi

发明人： Shigenobu Tanaka ,  Hikaru Yasuhara ,  Munesuke Oguchi

IPC分类号： G01R31/10 ,  G01R31/11 ,  G01R31/08

CPC分类号： G01R31/10 ,  G01R31/11

摘要： The distance from the end of the cable to the dielectric weak point of said cable is measured by applying a D.C. high voltage to said cable and generating a discharge at the dielectric weak point, obtaining a pair of pulse signals one by differentiating a surge signal generated and the other reflected at said dielectric weak point, limiting the amplitude of said pair of pulse signals, and measuring the interval between said pair of pulse signals.