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公开(公告)号：US20050068824A1
公开(公告)日：2005-03-31
申请号：US10935713
申请日：2004-09-08
IPC分类号： G11C11/413 , G11C5/14 , G11C11/41 , G11C11/417 , G11C7/00
CPC分类号： G11C11/417 , G11C5/146
摘要： A semiconductor memory of the present invention comprises: a static-type memory cell constituted of a pair of access transistors formed with NMOS transistors, a pair of drive transistors formed with NMOS transistors, and a pair of load transistors formed with PMOS transistors. Further, it comprises a substrate bias control unit which applies bias for increasing access speed to a substrate of any of the transistors when making access to the memory cell through adjusting electric current flown to a memory storage node in a common junction point of the three types of transistors. A substrate potential which is appropriate for reading-out, writing, memory-storing operation and low leak is applied.
摘要翻译： 本发明的半导体存储器包括：由NMOS晶体管形成的一对存取晶体管构成的静态型存储单元，由NMOS晶体管形成的一对驱动晶体管以及由PMOS晶体管形成的一对负载晶体管。 此外，它包括衬底偏置控制单元，当通过调节在三种类型的公共连接点中流向存储器存储节点的电流来访问存储单元时，施加偏置以增加对任何晶体管的衬底的访问速度 的晶体管。 适用于读出，写入，存储存储操作和低泄漏的衬底电位。
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公开(公告)号：US06982899B2
公开(公告)日：2006-01-03
申请号：US10752663
申请日：2004-01-08
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.
摘要翻译： 在一对位线之间提供虚拟位线。 一对位线被设定为电源电压，虚拟位线被设定为接地电压，然后使一对位线和虚拟位线相等。 当在随后的读取操作中激活字线时，一对位线处于低于电源电压的中间电位，使得存取晶体管的视在电流驱动能力降低，并且存储单元的静态噪声容限 增加
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公开(公告)号：US20060280009A1
公开(公告)日：2006-12-14
申请号：US11449606
申请日：2006-06-09
IPC分类号： G11C7/00
摘要： A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.
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公开(公告)号：US20050002225A1
公开(公告)日：2005-01-06
申请号：US10879753
申请日：2004-06-30
IPC分类号： G11C11/417 , G11C7/10 , G11C7/12 , G11C7/18 , G11C11/41 , G11C11/419 , G11C11/00
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/419 , G11C2207/002
摘要： A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.
摘要翻译： 半导体存储器件包括多个存储单元组。 每个存储单元组包括至少两个存储单元。 每个存储单元组包括读取部分和写入部分。 存储单元的数据通过读取部分从一个位线读取到读出的全局位线。 写入部分由相同存储器单元组中的至少两个存储器单元共享。 因此，尽管存储单元具有共同的6晶体管结构，但期望地将数据写入存储单元。
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公开(公告)号：US08045389B2
公开(公告)日：2011-10-25
申请号：US12949346
申请日：2010-11-18
IPC分类号： G11C11/34
CPC分类号： G11C5/063 , G11C7/14 , G11C11/417
摘要： A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.
摘要翻译： 在存储单元阵列中设置虚拟单元阵列，并且在输入/输出电路之间提供中间缓冲器，由此可以以高速和高频率操作输入/输出电路的控制信号，而区域增加效应为 甚至在具有大的位宽的存储器中也减少。
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公开(公告)号：US07054211B2
公开(公告)日：2006-05-30
申请号：US10732297
申请日：2003-12-11
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C7/14 , G11C2207/065
摘要： A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a plurality of word lines on the output side of each word line driver. The source of the n-channel transistor is connected through a selective switching element to the gate of the corresponding one of a plurality of replica transistors connected to a dummy bit line. The gate of each replica transistor is connected to the corresponding one of discharge transistors. The dummy bit line is connected to a sense amplifier through a logic gate.
摘要翻译： 公开了一种半导体存储器存储器，其中多个n沟道晶体管中的每一个的栅极连接到每个字线驱动器的输出侧上的多个字线中的相应一个字线。 n沟道晶体管的源极通过选择性开关元件连接到连接到虚拟位线的多个复制晶体管中的对应的一个的栅极。 每个复制晶体管的栅极连接到相应的一个放电晶体管。 虚拟位线通过逻辑门连接到读出放大器。
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公开(公告)号：US07580305B2
公开(公告)日：2009-08-25
申请号：US12078743
申请日：2008-04-04
IPC分类号： G11C7/00
摘要： A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.
摘要翻译： 半导体存储器包括：第一和第二位线; 预充电电路，用于将第一和第二位线预充电到预定电位; 每个连接到第一或第二位线的多个存储单元，所选择的一个存储器单元根据所选择的存储单元保持的信号维持或放电预充电的第一和第二位线之一; 用于选择存储单元的字线; 分别连接到第一和第二位线的第一和第二参考单元，第一和第二参考单元中选定的一个放电连接到所选参考单元的第一或第二位线; 以及分别用于选择第一和第二参考单元的第一和第二参考单元格字线。
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公开(公告)号：US20080259706A1
公开(公告)日：2008-10-23
申请号：US12078743
申请日：2008-04-04
IPC分类号： G11C7/00
摘要： A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.
摘要翻译： 半导体存储器包括：第一和第二位线; 预充电电路，用于将第一和第二位线预充电到预定电位; 每个连接到第一或第二位线的多个存储单元，所选择的一个存储器单元根据所选择的存储单元保持的信号维持或放电预充电的第一和第二位线之一; 用于选择存储单元的字线; 分别连接到第一和第二位线的第一和第二参考单元，第一和第二参考单元中选定的一个放电连接到所选参考单元的第一或第二位线; 以及分别用于选择第一和第二参考单元的第一和第二参考单元格字线。
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公开(公告)号：US07366037B2
公开(公告)日：2008-04-29
申请号：US11449606
申请日：2006-06-09
IPC分类号： G11C7/00
摘要： A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.
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公开(公告)号：US07136297B2
公开(公告)日：2006-11-14
申请号：US11075740
申请日：2005-03-10
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： An SRAM includes: a memory cell array; and a control circuit. Each memory cell includes: inverters; and access transistors interposed in lines connecting internal nodes in the respective inverters and a pair of bit lines BIT and NBIT. The control circuit includes a bias circuit for transmitting signals to the bit lines BIT and NBIT. A memory cell power supply terminal and a control circuit power supply terminal are isolated from each other. When power is turned on, the bias circuit sets one of the bit lines at a power supply potential (high potential) and the other bit line at a ground potential, so that a minute potential difference is generated between the internal nodes and thereby data is initialized. Transistors in the memory cell do not need to be asymmetric.
摘要翻译： SRAM包括：存储单元阵列; 和控制电路。 每个存储单元包括：逆变器; 以及插入在连接各个反相器中的内部节点的线路中的存取晶体管和一对位线BIT和NBIT。 控制电路包括用于向位线BIT和NBIT发送信号的偏置电路。 存储单元电源端子和控制电路电源端子彼此隔离。 当电源接通时，偏置电路将位线之一置于电源电位（高电位），另一位线处于接地电位，从而在内部节点之间产生微小的电位差，从而数据为 初始化 存储单元中的晶体管不需要是不对称的。
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