公开(公告)号：US06660593B2

公开(公告)日：2003-12-09

申请号：US09747374

申请日：2000-12-21

申请人： Shing-Sing Chiang ,  Kuo-Shi Teng ,  Hao-Chieh Yung ,  Yi-Shi Chen

发明人： Shing-Sing Chiang ,  Kuo-Shi Teng ,  Hao-Chieh Yung ,  Yi-Shi Chen

IPC分类号： H01L2100

CPC分类号： H01L21/823462 ,  H01L21/32

摘要： A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer. The substrate is oxidized to form a second oxide layer over the second active region, wherein the second oxide layer has a thickness different from the thickness of the first oxide layer,

公开(公告)号：US06200867B1

公开(公告)日：2001-03-13

申请号：US09192504

申请日：1998-11-17

申请人： Yi-Shi Chen

发明人： Yi-Shi Chen

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/41783 ,  H01L29/665

摘要： A method for forming self-aligned raised source and drain regions on a semiconductor wafer includes the steps of defining a substrate, growing a first layer of dielectric material over the substrate, depositing a layer of polysilicon over the first layer of dielectric material, patterning and forming at least one gate, depositing a second layer of dielectric material over the gate and the first dielectric layer and masking the second dielectric layer to define a source region and a drain region. The method also includes the steps of anisotropically etching to form sidewall spacers contiguous with the gate, collimated sputtering to deposit a layer of silicon, and implanting ions into the deposited silicon.

摘要翻译： 一种用于在半导体晶片上形成自对准凸起源极和漏极区域的方法包括以下步骤：限定衬底，在衬底上生长第一介电材料层，在第一绝缘材料层上沉积多晶硅层，图案化和 形成至少一个栅极，在所述栅极和所述第一电介质层上沉积第二介电材料层，并掩蔽所述第二电介质层以限定源极区域和漏极区域。 该方法还包括各向异性蚀刻以形成与栅极连接的侧壁间隔的步骤，准直溅射以沉积一层硅，以及将离子注入到沉积的硅中。

公开(公告)号：US06265272B1

公开(公告)日：2001-07-24

申请号：US09671592

申请日：2000-09-28

申请人： Yi-Shi Chen

发明人： Yi-Shi Chen

IPC分类号： H01L2100

CPC分类号： H01L29/665 ,  H01L29/66606

摘要： A fabrication process of forming a semiconductor device with elevated source/drain regions on a substrate is disclosed. The elevated portion of the source/drain regions is provided as a reactant for a later metallization process, thereby preventing the consumption of too much silicon contained in the source/drain regions. First, an elevated silicon layer is formed on portions of a substrate for forming source/drain regions of a semiconductor device. Next, a gate dielectric layer and a gate electrode layer are formed on the elevated silicon layer successively to construct a gate structure. Then, a lightly doped ion implantation process, a process of forming a sidewall spacer and a heavily doped ion implantation process are performed successively. Thus, the elevated silicon layer can be used as a reactant while performing a self-aligned silicidization process.

摘要翻译： 公开了一种在衬底上形成具有升高的源极/漏极区域的半导体器件的制造工艺。 源极/漏极区域的升高部分被提供为用于稍后的金属化工艺的反应物，从而防止在源极/漏极区域中包含的太多的硅的消耗。 首先，在用于形成半导体器件的源极/漏极区域的衬底的部分上形成升高的硅层。 接下来，在升高的硅层上依次形成栅介质层和栅极电极层以构成栅极结构。 然后，依次进行轻掺杂离子注入工艺，形成侧壁间隔物和重掺杂离子注入工艺。 因此，升高的硅层可以用作反应物，同时进行自对准硅化工艺。

公开(公告)号：US5780892A

公开(公告)日：1998-07-14

申请号：US758057

申请日：1996-11-27

申请人： Yi-Shi Chen

发明人： Yi-Shi Chen

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A floating gate E.sup.2 PROM cell is provided with a poly silicon floating gate having a pointed, sloped edge. A poly oxide is disposed on the pointed, sloped edge of the floating gate. A select gate is disposed on the poly oxide. The select gate overlaps the pointed, sloped edge of the floating gate. The floating gate, poly oxide, and select gate cooperate so that electrons tunnel according to enhanced Fowler Nordheim tunnelling from a point of the pointed, sloped edge of the floating gate, through the poly oxide and into the select gate. A simple process is also provided for fabricating an E.sup.2 PROM cell including the step of forming a nitride layer on a poly silicon layer. The nitride layer is patterned, using a photo-lithographic technique, to form an exposed poly silicon layer surface window. The exposed surface window of the poly silicon layer is then oxidized using a LOCOS (local oxidation of silicon) process to form a poly oxide region. The poly oxide region thus formed has a tapered edge which is adjacent to a pointed, sloped edge of a remaining non-oxidized poly silicon floating gate region of the poly silicon layer. A poly oxide layer is then formed on the poly silicon floating gate region. A select gate is then formed on the poly oxide layer so that it overlaps the pointed, sloped edge of the poly silicon floating gate.

摘要翻译： 浮动栅极E2PROM单元设置有具有尖的倾斜边缘的多晶硅浮动栅极。 多晶氧化物设置在浮动栅极的尖的倾斜边缘上。 选择栅极设置在多晶氧化物上。 选择栅极与浮动栅极的尖锐的倾斜边缘重叠。 浮动栅极，多晶氧化物和选择栅极配合使得电子根据增强的Fowler Nordheim隧道从浮动栅极的尖锐的边缘点穿过多孔氧化物并进入选择栅极。 还提供了一种用于制造E2PROM电池的简单工艺，包括在多晶硅层上形成氮化物层的步骤。 使用光刻技术将氮化物层图案化，以形成暴露的多晶硅层表面窗。 然后使用LOCOS（硅的局部氧化）工艺来氧化多晶硅层的暴露的表面窗口以形成多晶氧化物区域。 如此形成的多晶氧化物区域具有与多晶硅层的剩余未氧化多晶硅浮栅区域的尖锐边缘相邻的锥形边缘。 然后在多晶硅浮栅区域上形成多晶氧化层。 然后在多晶氧化物层上形成选择栅极，使其与多晶硅浮动栅极的尖锐的倾斜边缘重叠。